Hi are there any plans to fully support the mapping of input data to the same logical address as the outputs? The ESC Asic supports this through the LRW command and is already used by TwinCAT!
This would reduce the size of the sent/received ECAT frame almost by half: We have a refresh rate of 4kHz and control over 20 Servo devices with FSoE, so there is not much "space" to send multiple frames within 250µs. I researched the code a bit and realized that the FMMU setup could be changed so that successive FMMUs with opposite direction could use the same logical address as the previous configured FMMU. A more tricky problem is that the domain datagrams point directly to the domain data and that data is just memcpy-ed to/from the frame. Perhaps the domain FMMUs may be used to access just parts of the domain data. Regards Martin Martin Troxler Komax AG Note: This e-mail is for the named person's use only. It may contain confidential and/or privileged information. If you have received this e-mail in error, please notify the sender immediately and delete the material from any system. Any unauthorized copying, disclosure, distribution or other use of this information by persons or entities other than the intended recipient is prohibited. Thank You. _______________________________________________ etherlab-dev mailing list etherlab-dev@etherlab.org http://lists.etherlab.org/mailman/listinfo/etherlab-dev
