Hi Florian, I see you checked in some extra debugging on SII content a couple of weeks ago. Have you identified slaves with consistent SII issues, or are they intermittent? If they are intermittent then it may be due to the master reading the SII contents before the slave has completed finished reading it in from the EEPROM, so the master ends up getting garbage / uninitialized values.
If it's intermittent, I wrote a patch for Gavin's patchset which may help. The patch reorders the fsm_slave_scan states so that the datalink states (which read register 0x0110) are run before checking the dc registers (which may also be initialised from the EEPROM). This state now blocks until bit 0 is set (PDI operation/EEPROM loaded bit) and error's out if there is a timeout. Regards, Graeme Foot.
0002-retry-dc-register.patch
Description: 0002-retry-dc-register.patch
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