Hi： Thank you for the reply, I still have a problem: In the master code: the function "ec_fsm_slave_config_state_dc_sync_check" use the shift_time in the below code:
start = start_time +sync0->cycle_time - remainder + sync0->shift_time; I can't understand why add the sync0->shift_time to make the correct phase, there is no guidance to get the exact shift_time. -----邮件原件----- 发件人: [email protected] [mailto:[email protected]] 代表 Gavin Lambert 发送时间: 2016年4月15日 10:16 收件人: [email protected]; [email protected] 主题: RE: [etherlab-users] 答复: [SPAM] etherlab-users Digest, Vol 106, Issue 6 On Friday, 15 April 2016 13:49, quoth [email protected]: > When I use the interface function: ecrt_slave_config_dc(sc1, 0x0730, > 250000, 0, 1750000, 0); > > I can't understand the parameter "SYNC0 shift time" used in the master > module, in the master modules code , the "SYNC0 shift time" is used in > function "ec_fsm_slave_config_state_dc_sync_check" and the note is to "find > the correct phase", what's the exact meaning of "find the correct phase"? The shift time alters the phase (shifts the timing) between the SYNC0 signal and the target time for the EtherCAT domain datagram exchange. Exactly how this is affected and what values you should use depend on the cycle rate of your domain and the DC operation mode of the slave. Typically you should find guidance on what values to use in the slave vendor's datasheets or other documentation. You may also need to adjust it depending on the system jitter of your master PC. _______________________________________________ etherlab-users mailing list [email protected] http://lists.etherlab.org/mailman/listinfo/etherlab-users
