Hi, It is sounding like the data time on the wire is taking too long (> 250us).
Besides doubling the "DC system time transmission delay" of the last slave, you can also check the "Diff [ns]" value of your first slave. This may give you a more accurate idea if you have a star topology, as the return trip of the frame from the last slave bypasses the fingers of the stars. e.g.: ethercat slaves -v -p0 === Master 0, Slave 0 === Alias: 10001 Device: Main State: OP Flag: + Identity: Vendor Id: 0x00000002 Product code: 0x04562c52 Revision number: 0x00110000 Serial number: 0x00000000 DL information: FMMU bit operation: no Distributed clocks: yes, 64 bit DC system time transmission delay: 0 ns Port Type Link Loop Signal NextSlave RxTime [ns] Diff [ns] NextDc [ns] 0* EBUS up open yes - 3638440690 0 0 1 MII up open yes 1 3638442410 1720 560 2 N/A down closed no - - - - 3 N/C down closed no - - - - You will also need to add on 2 * "master to first slave transmission delay" which you will probably need to guess. If you use a Beckhoff CX2020 (or similar) where the CX2100 is directly connected to the EBus this will likely be around 150us. If your master has an ethernet port and the first slave is an amp or a coupler this may be around 550us or more (depending on cable length). You could also calc the frame transmission time. Your frame length is 782 bytes. So that should take ~ 6 - 7us. Plus whatever other overheads the ethernet card / driver has. Reducing the number of configured slaves (even with them still physically plugged in) will reduce the ec_master_domain_queue() and ec_master_send() overhead time, getting the frame to the wire quicker. It will also reduce the frame length and the related frame transmission time (especially if you remove slaves with bigger datagram overhead). It looks like this is enough to result in the total frame roundtrip time being reduce enough for it to return and be ready by the time that ec_master_receive() is called. Just FYI, I have a machine downstairs at the moment with 42 slaves (14 of which are amps), linear topology. The last slaves transmission delay is 19560ns. The first slaves Diff is 39390ns. The EtherCAT frame size is 886 bytes. The ec_master_receive() to ec_master_send() time is approx 23us. So your values sound in line with what I have, except that the wireshark output is showing a large cycle time. In general it's looking like the time on the wire is taking longer than it should. How are you capturing the EtherCAT frame data? e.g.: a switch between your master and first slave? If so, try moving it further down the chain, doing an "ethercat rescan" and check the transmission delays. See if the switch is causing a large delay between those slaves. What is your network card and driver used by the master? What is your realtime system? If you are using tshark on the master PC there might be delays being introduced in the network card driver. Regards, Graeme. From: etherlab-users <etherlab-users-boun...@etherlab.org> On Behalf Of Jordan Palacios Sent: Thursday, 31 October 2019 4:36 AM To: etherlab-users@etherlab.org Subject: [etherlab-users] Control loop at higher frequencies Hi. We've been working with the etherlab master for some time now. On our current setup we have around 40 slaves and our control loop runs at 1Khz without any issues. We use the stable version of etherlab with the 20180622 patchset. Recently we've tried increasing the loop frequency to achieve a better control. The target frequency is 4Khz. After some troubles we managed a stable control at 2Khz. Then we went for the 4Khz and this is where we have hit a roadblock. A warning like this is generated each second: [11547.183302] EtherCAT WARNING 0: 4000 datagrams UNMATCHED! [11547.619399] EtherCAT WARNING: Datagram ffff88040b6bf318 (domain0-0-main) was SKIPPED 4004 times. As per what Florian explained here<http://lists.etherlab.org/pipermail/etherlab-users/2009/000386.html> this means that the answer to the last datagram sent has not been received yet. I don't think this is related to the rate at which we execute the control loop. We have instrumented it and is steady at 250us with a jitter below 10us (see attachment). Furthermore, we have also enabled the ethercat master debug interface. Here is a sample of the traffic output using tshark: 7807 0.975750173 MS-NLB-PhysServer-19_95:2e:e1:b0 → Broadcast ECAT 810 'LRW': Len: 782, Adp 0x0, Ado 0x0, Wc 69 7808 0.975757725 Congatec_2e:e1:b0 → Broadcast ECAT 810 'LRW': Len: 782, Adp 0x0, Ado 0x0, Wc 0 7809 0.976000284 MS-NLB-PhysServer-19_95:2e:e1:b0 → Broadcast ECAT 810 'LRW': Len: 782, Adp 0x0, Ado 0x0, Wc 69 7810 0.976007872 Congatec_2e:e1:b0 → Broadcast ECAT 810 'LRW': Len: 782, Adp 0x0, Ado 0x0, Wc 0 7811 0.976252515 MS-NLB-PhysServer-19_95:2e:e1:b0 → Broadcast ECAT 810 'LRW': Len: 782, Adp 0x0, Ado 0x0, Wc 69 7812 0.976260050 Congatec_2e:e1:b0 → Broadcast ECAT 810 'LRW': Len: 782, Adp 0x0, Ado 0x0, Wc 0 The master received is done right at the beginning of the loop, and is followed by the domain process, domain queue and master send. The calculations are done after. We instrumented the received/send calls and we know together take around 20us. We originally made our calculations before the domain queue and master send. After reading what Graeme explains here<http://lists.etherlab.org/pipermail/etherlab-users/2018/003351.html> we changed the order to allow for more time for the data in the wire. This change helped achieving the 2Khz. All of this means that the time at which the frames are received is another good indicator of the correct control loop periodicity. Note also how the next frame is sent right after. Thing is, even though the WC is the expected (69 in this case), we think that these frames are always late. The datagram received is the one of the previous cycle. Hence the constant warning of 4000 datagrams skipped. The statistics reported by the "ethercat master" command show 4000 frames transmitted/received per second and no frames are lost. Checking the "DC system time transmission delay" of the last slave we get a value of 38995 ns, which would translate to something like 80us for the frame to be in the wire. Keeping in mind we are allowing for 230us for the datagram to return (250us cycle minus 20us for receive/send) it should be more than enough. Yet something doesn't add up. The only thing that seems to help is reducing the amount of slaves. If we switch to something like a 25 slave configuration then we manage to control at 4KHz without issues. We don't physically disconnect them though so the DC system time transmission delay remains the same. Obviously frame size is smaller. We are not performing any calls related to distributed clocks in the master. If I understand correctly DC are used for synchronizing the data processing of the slaves. It should not affect the frame delay, right? Any ideas are appreciated. Kind regards. Jordán. -- Jordán Palacios Software Engineer [https://lh6.googleusercontent.com/mgsVJlQ9p5jN1eI-8SP0YOxUhv0BEXrjZFnqqzYgaopfqhinUDbC7abJqhSV9RmgauHBXoff-GMTrJpOL2B9iYbSUgQN3cY8gIFI1XzcMdqZ6nG_Qera_i9qg2VQk35dG0uR01Ut] C/ Pujades 77-79, 4-4 08005 Barcelona, Spain Skype jordanpalacios.pal-robotics Tel +34 93 414 53 47<tel:%2B34%2093%20414%2053%2047> jordan.palac...@pal-robotics.com<mailto:jordan.palac...@pal-robotics.com> www.pal-robotics.com<http://www.pal-robotics.com/> Facebook<https://www.facebook.com/palrobotics/> | Twitter<https://twitter.com/PALRobotics> | YouTube<http://www.youtube.com/user/PALRobotics> | Blog<http://blog.pal-robotics.com/> AVISO DE CONFIDENCIALIDAD: Este mensaje y sus documentos adjuntos, pueden contener información privilegiada y/o confidencial que está dirigida exclusivamente a su destinatario. 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