On Sunday 20 May 2001 16:25, Daniel Munden wrote:
> On Sun, 20 May 2001, Civileme wrote:
> % You are looking at timing chatter under tightened timing requirements in
> % kernel 2.4. The solution is to relocate one of the drives to another
> channel % or simply throw it away. These timing requirements are
> necessary to avoid % data corruption in UDMA4 and 5 setups.
>
> As in first or secondary connector on the controller card?
>
> % A second item is that VIA chipsets are buggy, performing in logic race
> % fashion for IDE transfers and causing MASSIVE CORRUPTION for several
> hundred % megabyte cross-channel transfers under not only kernel 2.4 but
> also win2K and % ME. VIA has been working with board manufacturers to
> update the BIOS to % rearrange PCI resources. You may want to give the
> mainboard the most recent % BIOS the manufacturer has.
As in a flash to the most recent BIOS-- http://203.161.230.38/newbios2.html
has the flash utilities and an index to the models of board where the most
recent BIOSes can be retrieved. PCChips seems to have improved recently.
Civileme
>
> As in a EEPROM update or actually switch in a new chip?
>
> How do I contact VIA? I tried to get results from PCChips (the
> maker of my mainboard), but they don't respond whatsoever. Although,
> I do have some information that I gathered and need some help sorting
> it out.
>
> Note: When you reply to this message, please include the mailing
> list/newsgroup address and my email address in To:.
>
> *********************************************************************
> Signed,
> SoloCDM
