Does it depend on the processor? We have a double PII and a double Xeon
(which shows as 4 processor). On the PII, it is balanced, on the Xeon,
CPU0 does all the work.

Just wondering,
Guillaume.

On Thu, 2003-06-12 at 12:20, Mark Watts wrote:
> -----BEGIN PGP SIGNED MESSAGE-----
> Hash: SHA1
> 
> * IRQ balancing has been fixed for SMP
> 
> Incorrect.
> 
> [EMAIL PROTECTED] root]# uname -a
> Linux mail1 2.4.21-0.18mdkenterprise #1 SMP Wed Jun 4 11:44:12 MDT 2003 i686 
> unknown unknown GNU/Linux
> 
> [EMAIL PROTECTED] root]# cat /proc/interrupts
>            CPU0       CPU1
>   0:      46423          0    IO-APIC-edge  timer
>   1:          2          0    IO-APIC-edge  keyboard
>   2:          0          0          XT-PIC  cascade
>   5:          0          0   IO-APIC-level  usb-ohci
>   8:          1          0    IO-APIC-edge  rtc
>  14:          6          0    IO-APIC-edge  ide0
>  16:         16          0   IO-APIC-level  aic7xxx
>  17:         16          0   IO-APIC-level  aic7xxx
>  28:       5206          0   IO-APIC-level  eth0
>  29:       4179          0   IO-APIC-level  eth1
>  30:      11562          0   IO-APIC-level  aacraid
> NMI:          0          0
> LOC:      46328      46283
> ERR:          0
> MIS:          0
> 
> 
> 
> 
> - -- 
> Mark Watts
> Systems Engineer
> QinetiQ TIM
> St Andrews Road, Malvern
> GPG Public Key ID: 455420ED
> 
> -----BEGIN PGP SIGNATURE-----
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> 
> iD8DBQE+6KheBn4EFUVUIO0RAun7AJ9wqckUCJdzLFaHCMb/Y4GDvKWJYQCeOQLE
> Imrck9wxxvfrCQOygO62rCI=
> =bCFF
> -----END PGP SIGNATURE-----
> 
> 
> ----
> 

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