Hi, I checked again and ...
if eflags xor 200000h has an effect, then CPUID is possible, which is
the case on most 486. On the Cyrix 6x86, CPUID -and- the reaction on
eflags xor 200000h are off by default, but I do:

ndisasm -b16 -o256 tune_cx.com 
00000100  BE1201            mov si,0x112
00000103  AD                lodsw
00000104  09C0              or ax,ax
00000106  7502              jnz 0x10a
00000108  CD20              int 0x20
0000010A  E622              out 0x22,al
0000010C  88E0              mov al,ah
0000010E  E623              out 0x23,al
00000110  EBF1              jmp short 0x103
00000112  dw 10c3, 90e8, 720, 92c1, cac2, ddc, fe3, 6fc, 99fd, 0

And before of that, I do:

00000100  B80000            mov ax,0x0
00000103  BF0002            mov di,0x200
00000106  86C4              xchg al,ah
00000108  E622              out 0x22,al
0000010A  40                inc ax
0000010B  86C4              xchg al,ah
0000010D  E423              in al,0x23
0000010F  AA                stosb
00000110  08E4              or ah,ah
00000112  75F2              jnz 0x106
00000114  B0C3              mov al,0xc3
00000116  E622              out 0x22,al
00000118  EB00              jmp short 0x11a
0000011A  E423              in al,0x23
0000011C  50                push ax
0000011D  240F              and al,0xf
0000011F  0C10              or al,0x10
00000121  50                push ax
00000122  B0C3              mov al,0xc3
00000124  E622              out 0x22,al
00000126  58                pop ax
00000127  E623              out 0x23,al
00000129  B0E8              mov al,0xe8
0000012B  E622              out 0x22,al
0000012D  EB00              jmp short 0x12f
0000012F  E423              in al,0x23
00000131  0C80              or al,0x80
00000133  50                push ax
00000134  B0E8              mov al,0xe8
00000136  E622              out 0x22,al
00000138  58                pop ax
00000139  E623              out 0x23,al
0000013B  B0C3              mov al,0xc3
0000013D  E622              out 0x22,al
0000013F  58                pop ax
00000140  E623              out 0x23,al
00000142  EB2C              jmp short 0x170
...
00000170  6631C0            xor eax,eax
00000173  0FA2              cpuid
00000175  89C5              mov bp,ax
00000177  31F6              xor si,si
00000179  6631C0            xor eax,eax
0000017C  89F0              mov ax,si
0000017E  0FA2              cpuid
00000180  66AB              stosd
00000182  6689D8            mov eax,ebx
00000185  66AB              stosd
00000187  6689D0            mov eax,edx
0000018A  66AB              stosd
0000018C  6689C8            mov eax,ecx
0000018F  66AB              stosd
00000191  46                inc si
00000192  39EE              cmp si,bp
00000194  76E3              jna 0x179
00000196  B84541            mov ax,0x4145
00000199  AB                stosw
0000019A  AB                stosw
0000019B  BE0403            mov si,0x304
0000019E  B90C00            mov cx,0xc
000001A1  BFF001            mov di,0x1f0
000001A4  F3A4              rep movsb
000001A6  BAE001            mov dx,0x1e0
000001A9  B409              mov ah,0x9
000001AB  CD21              int 0x21
000001AD  B8004C            mov ax,0x4c00
000001B0  CD21              int 0x21
...
000001E0  db "AuerSoft CPUID:'"
000001F0  db "############',13,10,"$"

I hope anybody who is also using a Cyrix 6x86 has some fun with
the above code...

The short program enables some optimization settings, and the longer
program enables CPUID and prints the string returned by CPUID then.

I found some very detailed information in the datasheet collection of
www.conrad.de -> ST6x86 is sold as part no. 178080, and there is an
178080-da-01-en-ST6x86.pdf ... or two of them (390455 and 1698934 bytes),
53 and 240 pages. However, the TSC is not mentioned (not even its non-
existence in that 6x86s...). But CPUID is, in the shorter document, page
25: CCR4 has the ID enable bit in the most significant bit.
CCR4 is the configuration register with index e8, and in order to be able
to set THAT register, register c3 must be 0001xxxx (binary). c3 is the CCR3
(configuration control 3) register: the high nibble of it is "MAPEN", which
currently can only be 0 or 1 (0 only allows accessing registers c0-cf,fe,ff).

The longer doc is generally interesting for people who want to program on
Pentium level, although for example the instruction timing is of course
different from a real Pentium in 6x86.

Back to RDTSC:
http://www.sandpile.org/ia32/cpuid.htm tells us that the availability of
MSR, TSC and TSD (linked from there) can be detected by checking a bit
which PCTEST fails to test (in the bits returned by CPUID).
However, details are not explained there :-(. But the Linux Kernel Archive
tells us more :-). You can modify the TSC flag in CR4 to enable / disable
the privilege protection of RDTSC: When protected, only CPL0 may access TSC.

http://www.uwsg.iu.edu/hypermail/linux/kernel/9703.0/0006.html

By the way, I think I have an M1 aka. 6x86 - the M2 has TSC and MMX, but
my chip has neither.

This and more is detailed in:
http://thorkildsen.no/faqsys/docs/pentium.txt :-).

Eric

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