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new d9e8c85617 swscale/x86/ops_int: Check for cpuflag instead of
avx_enabled
d9e8c85617 is described below
commit d9e8c856171834be8fe20fde0ed991e96f84acf0
Author: Andreas Rheinhardt <[email protected]>
AuthorDate: Wed Jan 21 11:50:24 2026 +0100
Commit: Andreas Rheinhardt <[email protected]>
CommitDate: Mon Jan 26 13:10:15 2026 +0100
swscale/x86/ops_int: Check for cpuflag instead of avx_enabled
This would make this code compatible with forcing VEX encodings
for the SSE4 codepath and is also more correct, because avx_enabled
would be enabled for AVX, although the instructions used in these
codepaths require AVX2.
Reviewed-by: Niklas Haas <[email protected]>
Signed-off-by: Andreas Rheinhardt <[email protected]>
---
libswscale/x86/ops_int.asm | 25 ++++++++++---------------
1 file changed, 10 insertions(+), 15 deletions(-)
diff --git a/libswscale/x86/ops_int.asm b/libswscale/x86/ops_int.asm
index fa7b13cd25..edfbabb60d 100644
--- a/libswscale/x86/ops_int.asm
+++ b/libswscale/x86/ops_int.asm
@@ -284,7 +284,7 @@ IF %1 < 32, VBROADCASTI128 m12, [read%1_unpack2]
unpckhpd my, m8, m9 ; { Y0 Y2 | Y1 Y3 }
IF V2, unpcklpd mx2, m10, m11
IF V2, unpckhpd my2, m10, m11
-%if avx_enabled
+%if cpuflag(avx2)
vpermq mx, mx, q3120 ; { X0 X1 | X2 X3 }
vpermq my, my, q3120 ; { Y0 Y1 | Y2 Y3 }
IF V2, vpermq mx2, mx2, q3120
@@ -297,7 +297,7 @@ IF %1 < 32, VBROADCASTI128 m12, [read%1_unpack2]
op write%1_packed2
IF %1 < 32, VBROADCASTI128 m12, [write%1_pack2]
LOAD_CONT tmp0q
-%if avx_enabled
+%if cpuflag(avx2)
vpermq mx, mx, q3120 ; { X0 X2 | X1 X3 }
vpermq my, my, q3120 ; { Y0 Y2 | Y1 Y3 }
IF V2, vpermq mx2, mx2, q3120
@@ -332,7 +332,7 @@ IF V2, movu [out0q + 3*mmsize], m11
movu xm9, [%5 + 4 * %6]
movu xm10, [%5 + 8 * %6]
movu xm11, [%5 + 12 * %6]
- %if avx_enabled
+ %if cpuflag(avx2)
vinserti128 m8, m8, [%5 + 16 * %6], 1
vinserti128 m9, m9, [%5 + 20 * %6], 1
vinserti128 m10, m10, [%5 + 24 * %6], 1
@@ -393,7 +393,7 @@ IF1 V2, read_packed_inner mx2, my2, mz2, mw2, in0q + %1
* mmsize, %1, %2
movu [%5 + 4*%6], xm9
movu [%5 + 8*%6], xm10
movu [%5 + 12*%6], xm11
- %if avx_enabled
+ %if cpuflag(avx2)
vextracti128 [%5 + 16*%6], m8, 1
vextracti128 [%5 + 20*%6], m9, 1
vextracti128 [%5 + 24*%6], m10, 1
@@ -422,7 +422,7 @@ IF1 V2, write_packed_inner mx2, my2, mz2, mw2, out0q +
%1 * mmsize, %1, %2
%macro read_nibbles 0
op read_nibbles1
-%if avx_enabled
+%if cpuflag(avx2)
movu xmx, [in0q]
IF V2, movu xmx2, [in0q + 16]
%else
@@ -447,7 +447,7 @@ IF V2, por mx2, my2
%macro read_bits 0
op read_bits1
-%if avx_enabled
+%if cpuflag(avx2)
vpbroadcastd mx, [in0q]
IF V2, vpbroadcastd mx2, [in0q + 4]
%else
@@ -481,13 +481,8 @@ IF V2, psllw mx2, 7
IF V2, pshufb mx2, m8
pmovmskb tmp0d, mx
IF V2, pmovmskb tmp1d, mx2
-%if avx_enabled
mov [out0q], tmp0d
-IF V2, mov [out0q + 4], tmp1d
-%else
- mov [out0q], tmp0d
-IF V2, mov [out0q + 2], tmp1d
-%endif
+IF V2, mov [out0q + (mmsize >> 3)], tmp1d
LOAD_CONT tmp0q
add out0q, (mmsize >> 3) * (1 + V2)
FINISH tmp0q
@@ -599,12 +594,12 @@ IF V2, mova %3, %2
%macro clear_generic 0
op clear
LOAD_CONT tmp0q
-%if avx_enabled
+%if cpuflag(avx2)
IF !X, vpbroadcastd mx, [implq + SwsOpImpl.priv + 0]
IF !Y, vpbroadcastd my, [implq + SwsOpImpl.priv + 4]
IF !Z, vpbroadcastd mz, [implq + SwsOpImpl.priv + 8]
IF !W, vpbroadcastd mw, [implq + SwsOpImpl.priv + 12]
-%else ; !avx_enabled
+%else ; !cpuflag(avx2)
IF !X, movd mx, [implq + SwsOpImpl.priv + 0]
IF !Y, movd my, [implq + SwsOpImpl.priv + 4]
IF !Z, movd mz, [implq + SwsOpImpl.priv + 8]
@@ -802,7 +797,7 @@ op swizzle_1000
op %1_U8_U16
LOAD_CONT tmp0q
%if V2
- %if avx_enabled
+ %if cpuflag(avx2)
IF X, vextracti128 xmx2, mx, 1
IF Y, vextracti128 xmy2, my, 1
IF Z, vextracti128 xmz2, mz, 1
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