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commit 2a09d0346e9ea02547b98b7d3a9eaf01e574d265 Author: Niklas Haas <[email protected]> AuthorDate: Fri May 1 17:42:55 2026 +0200 Commit: Niklas Haas <[email protected]> CommitDate: Tue Jun 9 18:27:20 2026 +0200 swscale/x86/ops_include: clarify/fix some comments Signed-off-by: Niklas Haas <[email protected]> --- libswscale/x86/ops_include.asm | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/libswscale/x86/ops_include.asm b/libswscale/x86/ops_include.asm index d0b45b5f9e..dcbf5d8eaa 100644 --- a/libswscale/x86/ops_include.asm +++ b/libswscale/x86/ops_include.asm @@ -45,7 +45,7 @@ ; - bxd, yd: current line and block number, used as loop counters in sws_process. ; Also used by e.g. the dithering code to do position-dependent dithering. ; -; - tmp0, tmp1: two temporary registers which are NOT preserved between kernels +; - tmp0, tmp1, tmp2: temporary registers which are NOT preserved between kernels ; ; - inNq, outNq: plane pointers. These are incremented automatically after the ; corresponding read/write operation, by the read/write kernels themselves. @@ -62,8 +62,8 @@ ; The "high half" registers are only sometimes used; in order to enable ; processing more pixels at the same time. See `decl_v2` below, which allows ; assembling the same operation twice, once with only the lower half (V2=0), -; and once with both halves (V2=1). The remaining vectors are free for use -; inside operation kernels, starting from m8. +; and once with both halves (V2=1). The remaining vectors (m8-m15) are free for +; use inside operation kernels. ; ; The basic rule is that we always use the full set of both vector registers ; when processing the largest element size within a pixel chain. For example, _______________________________________________ ffmpeg-cvslog mailing list -- [email protected] To unsubscribe send an email to [email protected]
