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commit ecba7e1d42913cb9d8300957917b9b256413c586 Author: Ramiro Polla <[email protected]> AuthorDate: Mon Apr 13 15:14:29 2026 +0200 Commit: Ramiro Polla <[email protected]> CommitDate: Wed Jun 10 01:46:29 2026 +0200 swscale/aarch64/rasm: split conditional and unconditional branch instructions Sponsored-by: Sovereign Tech Fund Signed-off-by: Ramiro Polla <[email protected]> --- libswscale/aarch64/rasm.h | 36 +++++++++++++++++++----------------- libswscale/aarch64/rasm_print.c | 3 ++- 2 files changed, 21 insertions(+), 18 deletions(-) diff --git a/libswscale/aarch64/rasm.h b/libswscale/aarch64/rasm.h index 5a14d8cd64..a91fc3f291 100644 --- a/libswscale/aarch64/rasm.h +++ b/libswscale/aarch64/rasm.h @@ -248,6 +248,7 @@ typedef enum AArch64InsnId { AARCH64_INSN_ADR, AARCH64_INSN_AND, AARCH64_INSN_B, + AARCH64_INSN_BCOND, AARCH64_INSN_BR, AARCH64_INSN_CMP, AARCH64_INSN_CSEL, @@ -537,7 +538,8 @@ static inline RasmOp a64cond_nv(void) { return a64op_cond(AARCH64_COND_NV); } #define i_addv(rctx, op0, op1 ) rasm_add_insn(rctx, AARCH64_INSN_ADDV, op0, op1, OPN, OPN) #define i_adr(rctx, op0, op1 ) rasm_add_insn(rctx, AARCH64_INSN_ADR, op0, op1, OPN, OPN) #define i_and(rctx, op0, op1, op2 ) rasm_add_insn(rctx, AARCH64_INSN_AND, op0, op1, op2, OPN) -#define i_b(rctx, op0, op1 ) rasm_add_insn(rctx, AARCH64_INSN_B, op0, op1, OPN, OPN) +#define i_b(rctx, op0 ) rasm_add_insn(rctx, AARCH64_INSN_B, op0, OPN, OPN, OPN) +#define i_bcond(rctx, op0, op1 ) rasm_add_insn(rctx, AARCH64_INSN_BCOND, op0, op1, OPN, OPN) #define i_br(rctx, op0 ) rasm_add_insn(rctx, AARCH64_INSN_BR, op0, OPN, OPN, OPN) #define i_cmp(rctx, op0, op1 ) rasm_add_insn(rctx, AARCH64_INSN_CMP, op0, op1, OPN, OPN) #define i_csel(rctx, op0, op1, op2, op3) rasm_add_insn(rctx, AARCH64_INSN_CSEL, op0, op1, op2, op3) @@ -592,22 +594,22 @@ static inline RasmOp a64cond_nv(void) { return a64op_cond(AARCH64_COND_NV); } #define i_zip2(rctx, op0, op1, op2 ) rasm_add_insn(rctx, AARCH64_INSN_ZIP2, op0, op1, op2, OPN) /* Branch helpers. */ -#define i_beq(rctx, id) i_b(rctx, a64cond_eq(), rasm_op_label(id)) -#define i_bne(rctx, id) i_b(rctx, a64cond_ne(), rasm_op_label(id)) -#define i_bhs(rctx, id) i_b(rctx, a64cond_hs(), rasm_op_label(id)) -#define i_bcs(rctx, id) i_b(rctx, a64cond_cs(), rasm_op_label(id)) -#define i_blo(rctx, id) i_b(rctx, a64cond_lo(), rasm_op_label(id)) -#define i_bcc(rctx, id) i_b(rctx, a64cond_cc(), rasm_op_label(id)) -#define i_bmi(rctx, id) i_b(rctx, a64cond_mi(), rasm_op_label(id)) -#define i_bpl(rctx, id) i_b(rctx, a64cond_pl(), rasm_op_label(id)) -#define i_bvs(rctx, id) i_b(rctx, a64cond_vs(), rasm_op_label(id)) -#define i_bvc(rctx, id) i_b(rctx, a64cond_vc(), rasm_op_label(id)) -#define i_bhi(rctx, id) i_b(rctx, a64cond_hi(), rasm_op_label(id)) -#define i_bls(rctx, id) i_b(rctx, a64cond_ls(), rasm_op_label(id)) -#define i_bge(rctx, id) i_b(rctx, a64cond_ge(), rasm_op_label(id)) -#define i_blt(rctx, id) i_b(rctx, a64cond_lt(), rasm_op_label(id)) -#define i_bgt(rctx, id) i_b(rctx, a64cond_gt(), rasm_op_label(id)) -#define i_ble(rctx, id) i_b(rctx, a64cond_le(), rasm_op_label(id)) +#define i_beq(rctx, id) i_bcond(rctx, a64cond_eq(), rasm_op_label(id)) +#define i_bne(rctx, id) i_bcond(rctx, a64cond_ne(), rasm_op_label(id)) +#define i_bhs(rctx, id) i_bcond(rctx, a64cond_hs(), rasm_op_label(id)) +#define i_bcs(rctx, id) i_bcond(rctx, a64cond_cs(), rasm_op_label(id)) +#define i_blo(rctx, id) i_bcond(rctx, a64cond_lo(), rasm_op_label(id)) +#define i_bcc(rctx, id) i_bcond(rctx, a64cond_cc(), rasm_op_label(id)) +#define i_bmi(rctx, id) i_bcond(rctx, a64cond_mi(), rasm_op_label(id)) +#define i_bpl(rctx, id) i_bcond(rctx, a64cond_pl(), rasm_op_label(id)) +#define i_bvs(rctx, id) i_bcond(rctx, a64cond_vs(), rasm_op_label(id)) +#define i_bvc(rctx, id) i_bcond(rctx, a64cond_vc(), rasm_op_label(id)) +#define i_bhi(rctx, id) i_bcond(rctx, a64cond_hi(), rasm_op_label(id)) +#define i_bls(rctx, id) i_bcond(rctx, a64cond_ls(), rasm_op_label(id)) +#define i_bge(rctx, id) i_bcond(rctx, a64cond_ge(), rasm_op_label(id)) +#define i_blt(rctx, id) i_bcond(rctx, a64cond_lt(), rasm_op_label(id)) +#define i_bgt(rctx, id) i_bcond(rctx, a64cond_gt(), rasm_op_label(id)) +#define i_ble(rctx, id) i_bcond(rctx, a64cond_le(), rasm_op_label(id)) /* Extra helpers. */ #define i_mov16b(rctx, op0, op1) i_mov(rctx, v_16b(op0), v_16b(op1)) diff --git a/libswscale/aarch64/rasm_print.c b/libswscale/aarch64/rasm_print.c index 86f543b3c9..8f55d87401 100644 --- a/libswscale/aarch64/rasm_print.c +++ b/libswscale/aarch64/rasm_print.c @@ -271,6 +271,7 @@ static const char insn_names[AARCH64_INSN_NB][8] = { [AARCH64_INSN_ADR ] = "adr", [AARCH64_INSN_AND ] = "and", [AARCH64_INSN_B ] = "b", + [AARCH64_INSN_BCOND ] = "b", [AARCH64_INSN_BR ] = "br", [AARCH64_INSN_CMP ] = "cmp", [AARCH64_INSN_CSEL ] = "csel", @@ -342,7 +343,7 @@ static void print_node_insn(const RasmContext *rctx, indent_to(fp, pos, line_start, INSTR_INDENT); int op_start = 0; - if (node->insn.id == AARCH64_INSN_B && rasm_op_type(node->insn.op[0]) == AARCH64_OP_COND) { + if (node->insn.id == AARCH64_INSN_BCOND) { pos_fprintf(fp, pos, "b.%-14s", cond_name(a64op_cond_val(node->insn.op[0]))); op_start = 1; } else if (rasm_op_type(node->insn.op[0]) == RASM_OP_NONE) { _______________________________________________ ffmpeg-cvslog mailing list -- [email protected] To unsubscribe send an email to [email protected]
