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new 9862dd83b1 avcodec/aarch64/vc1dsp_neon: reduce literal pool alignment
to 16 bytes
9862dd83b1 is described below
commit 9862dd83b1645b0c6e39b318aefb896138ffb08e
Author: Kacper Michajłow <[email protected]>
AuthorDate: Thu Jul 30 14:00:33 2026 +0200
Commit: Kacper Michajłow <[email protected]>
CommitDate: Mon Aug 3 18:16:24 2026 +0000
avcodec/aarch64/vc1dsp_neon: reduce literal pool alignment to 16 bytes
armasm64 warns "A4228: Alignment value exceeds AREA alignment; alignment
not guaranteed" on the .Lcoeffs literal pool. gas-preprocessor.pl emits
the text section as "AREA |.text|, CODE, READONLY, ALIGN=4", i.e. a
16-byte section alignment, so a 32-byte ALIGN inside it cannot be
guaranteed by the assembler.
16 is enough here: the pool holds .quad values that are read with
"ldr d0, .Lcoeffs" literal loads, which only require 8-byte alignment.
It also matches the rest of the aarch64 asm, where the function and
const macros both default to .align 4.
Signed-off-by: Kacper Michajłow <[email protected]>
---
libavcodec/aarch64/vc1dsp_neon.S | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/libavcodec/aarch64/vc1dsp_neon.S b/libavcodec/aarch64/vc1dsp_neon.S
index 9a96c2523c..d8e7788026 100644
--- a/libavcodec/aarch64/vc1dsp_neon.S
+++ b/libavcodec/aarch64/vc1dsp_neon.S
@@ -696,7 +696,7 @@ function ff_vc1_inv_trans_4x4_dc_neon, export=1
ret
endfunc
-.align 5
+.align 4
.Lcoeffs_it8:
.quad 0x000F00090003
.Lcoeffs_it4:
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