From: Shivraj Patil <shivraj.pa...@imgtec.com> --- configure | 46 ++++++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 46 insertions(+)
diff --git a/configure b/configure index 4827a4d..8ddc604 100755 --- a/configure +++ b/configure @@ -361,6 +361,7 @@ Optimization options (experts only): --disable-yasm disable use of nasm/yasm assembly --disable-mipsdspr1 disable MIPS DSP ASE R1 optimizations --disable-mipsdspr2 disable MIPS DSP ASE R2 optimizations + --disable-msa disable MSA optimizations --disable-mipsfpu disable floating point MIPS optimizations --disable-fast-unaligned consider unaligned accesses slow @@ -1564,6 +1565,7 @@ ARCH_EXT_LIST_MIPS=" mips32r2 mipsdspr1 mipsdspr2 + msa " ARCH_EXT_LIST_X86_SIMD=" @@ -2003,6 +2005,7 @@ map 'eval ${v}_inline_deps=inline_asm' $ARCH_EXT_LIST_ARM mipsfpu_deps="mips" mipsdspr1_deps="mips" mipsdspr2_deps="mips" +msa_deps="mips" altivec_deps="ppc" ppc4xx_deps="ppc" @@ -3825,20 +3828,52 @@ elif enabled mips; then disable mipsfpu disable mipsdspr1 disable mipsdspr2 + disable msa ;; 24kf*) disable mipsdspr1 disable mipsdspr2 + disable msa ;; 24kec|34kc|1004kc) disable mipsfpu disable mipsdspr2 + disable msa ;; 24kef*|34kf*|1004kf*) disable mipsdspr2 + disable msa ;; 74kc) disable mipsfpu + disable mipsdspr1 + disable msa + ;; + p5600) + disable mips32r2 + disable mipsdspr1 + disable mipsdspr2 + enable mips32r5 + + add_cflags "-mtune=p5600" && add_asflags "-mtune=p5600" && add_ldflags "-march=p5600" + ;; + i6400) + disable mips32r2 + disable mipsdspr1 + disable mipsdspr2 + disable mipsfpu + enable mips64r6 + + add_cflags "-mtune=i6400" && add_asflags "-mtune=i6400" && add_ldflags "-march=i6400" + ;; + *) + disable mipsfpu + disable mips32r2 + disable mipsdspr1 + disable mipsdspr2 + disable mips32r5 + disable mips64r6 + disable msa ;; esac @@ -4594,16 +4629,26 @@ elif enabled mips; then add_cflags "-mips64" add_asflags "-mips64" elif enabled mipsfpu || enabled mipsdspr1 || enabled mipsdspr2; then + if [ "$cpu" != p5600 ] && ["$cpu" != i6400 ]; then add_cflags "-mips32r2" add_asflags "-mips32r2" + fi fi + enabled mips32r5 && add_cflags "-mips32r5 -msched-weight -mload-store-pairs -funroll-loops -mfp64" && + add_asflags "-mips32r5 -mfp64" && add_ldflags "-mips32r5 -mfp64" && + check_inline_asm mips32r5 '"rotr $t0, $t1, 1"' + enabled mips64r6 && add_cflags "-mips64r6 -msched-weight -mload-store-pairs -funroll-loops -mabi=64" && + add_ldflags "-mips64r6 -mabi=64" && add_asflags "-mips64r6 -mabi=64" && + check_inline_asm mips64r6 '"aui $t0, $t1, 1"' enabled mipsdspr1 && add_cflags "-mdsp" && add_asflags "-mdsp" && check_inline_asm mipsdspr1 '"addu.qb $t0, $t1, $t2"' enabled mipsdspr2 && add_cflags "-mdspr2" && add_asflags "-mdspr2" && check_inline_asm mipsdspr2 '"absq_s.qb $t0, $t1"' enabled mipsfpu && add_cflags "-mhard-float" && add_asflags "-mhard-float" && check_inline_asm mipsfpu '"madd.d $f0, $f2, $f4, $f6"' + enabled msa && add_cflags "-mmsa -mfp64 -flax-vector-conversions" && add_ldflags "-mmsa -mfp64" && + check_inline_asm msa '"addvi.b $w0, $w1, 1"' elif enabled parisc; then @@ -5556,6 +5601,7 @@ if enabled mips; then echo "MIPS FPU enabled ${mipsfpu-no}" echo "MIPS DSP R1 enabled ${mipsdspr1-no}" echo "MIPS DSP R2 enabled ${mipsdspr2-no}" + echo "MIPS MSA enabled ${msa-no}" fi if enabled ppc; then echo "AltiVec enabled ${altivec-no}" -- 2.3.2 _______________________________________________ ffmpeg-devel mailing list ffmpeg-devel@ffmpeg.org http://ffmpeg.org/mailman/listinfo/ffmpeg-devel