1.no longer use register name directly and optimized code format 2.to be compatibal with O32, specify type of address variable with mips_reg and handle the address varialbe with PTR_ operator 3.optimize some unalignment faults in load and store 4.use uld and mtc1 to workaround cpu 3A2000 gslwlc1 bug (gslwlc1 instruction extension bug in O32 ABI)
At 2016-05-15 01:56:34, "Michael Niedermayer" <mich...@niedermayer.cc> wrote: >On Fri, May 13, 2016 at 06:03:27PM +0800, 周晓勇 wrote: >> From 4adf70c0eb9a85fe6cbedb043ed8ce08024c48dc Mon Sep 17 00:00:00 2001 >> From: ZhouXiaoyong <zhouxiaoy...@loongson.cn> >> Date: Sat, 7 May 2016 14:16:28 +0800 > >> Subject: [PATCH 03/11] avcodec/mips: loongson optimize h264dsp with mmi v2 > >please provide more verbose commit messages >A commit message should state >what is changed >why it is changed >how it is changed >as well as what effects that has on user, compatibility, performance, ... > >[...] >-- >Michael GnuPG fingerprint: 9FF2128B147EF6730BADF133611EC787040B0FAB > >Those who are best at talking, realize last or never when they are wrong. _______________________________________________ ffmpeg-devel mailing list ffmpeg-devel@ffmpeg.org http://ffmpeg.org/mailman/listinfo/ffmpeg-devel
