Carl-Daniel Hailfinger wrote: > On 16.09.2009 19:07, Stefan Reinauer wrote: > >> Carl-Daniel Hailfinger wrote: >> >> >>> For optimal partial reflashing, we have to find out which parts of the >>> chip can be written without erase. For that, the only criterion (except >>> a limit on the number of writes for very old chips) is whether the write >>> will only clear bits (set them to 0). >>> If (current&new==new) we can skip the erase. >>> If any bit would have to be set to 1, we need to erase. >>> >>> >>> >>> >> Is that sufficient? Ie is it always ok to skip an erase if we're only >> clearing bits? >> >> > > It depends on the chip, but given that the following appears in the ICH7 > and all later datasheets as absolute flash requirement, I'm positive > most current flash chips support it. > > ----------------- > The system BIOS and Intel® Active Management Technology firmware usage > models > require that the serial flash device support multiple writes (minimum of > 512 writes) to > a page (256 bytes) without requiring a preceding erase command. > ----------------- > That means you can theoretically write it twice (2*256 byte writes on an x8 device) without erasing it. I don't think this is something we should rely on.
It also says serial flash device, which implies that LPC/FWH might behave differently. Stefan _______________________________________________ flashrom mailing list [email protected] http://www.flashrom.org/mailman/listinfo/flashrom
