Hi. I downloaded the latest snapshot of flashrom as you suggested, and you will find the new log in the attached file. There is yet a lot of "opcode 0x06 will be run as PREOP" lines: I deleted all of them but the first sequences. If you need them, let me known. I can rerun the program anytime, and if this little job can help you, I will do it.
About the code for the PentiumM/82855GME: I'm sorry, but I have nothing to submit. Is was a my personal attempt to port linuxbios, but the activity was (too soon ?) stopped. The development tree was moved into the "old things limbo", from where it was deleted by a mistyped answer during disk maintenance. Anyway, thanks. Regards Maurizio Cavalli Sviluppo Software CONTROL SYSTEMS S.r.l. Via del Brolo, 14 26100 CREMONA (Italy) tel +39 0372 471806 fax +39 0372 471823 www.controlsystems-srl.it -----Original Message----- From: Carl-Daniel Hailfinger [mailto:[email protected]] Sent: Fri 10/16/2009 12:45 PM To: Maurizio Cavalli Cc: [email protected] Subject: Re: [flashrom] Winbond W25X16 successful programming Hi Maurizio, thank you for your report. I will add your chip to the supported list. On 16.10.2009 10:03, Maurizio Cavalli wrote: > I had successfully programmed a Winbond W25X16(BVSSIG) chip with flashrom. > > Board: ROE RIVER Evaluation Board from Intel > (Reference: Intel® AtomTM Processor N270 and Mobile Intel® 945GSE Express > Chipset Development Kit User's Manual - Document number: 320436-002) > BIOS: Phoenix Embedded BIOS(R) w/StrongFrame(R) Technology. > Kernel: Linux 2.6.30.2 SMP, compiled from source tree > Host system: Debian 5.0 > The log of your flashrom version had thousands of lines like this: Invalid OPCODE 0x06 due to SPI master limitation, ignoring and hoping it will be run as PREOP I have removed them from your log to make the mail smaller. It would be great if you could test erase and write with the latest flashrom from svn as well. The invalid opcode messages should have disappeared. > (I apologize we cannot use coreboot because lack of chipsets documentation > from Intel. We already tried to port linuxBios onto a PentiumM/82855GME > platform, but we failed in setting up the integrated graphic controller) > Oh, that is interesting. So you do already have some code, but it is not working yet? Could you please send that code to the coreboot mailing list <[email protected]> so other developers can have a look. Maybe someone has good docs for that platform. Regards, Carl-Daniel -- Developer quote of the week: "We are juggling too many chainsaws and flaming arrows and tigers."
# flashrom -wV -c W25x16 cronos2m.bin > /tmp/flashrom-r750.log flashrom v0.9.1-r750 No coreboot table found. Found chipset "Intel ICH7M", enabling flash write... 0xfff80000/0xffb80000 FWH IDSEL: 0x0 0xfff00000/0xffb00000 FWH IDSEL: 0x0 0xffe80000/0xffa80000 FWH IDSEL: 0x1 0xffe00000/0xffa00000 FWH IDSEL: 0x1 0xffd80000/0xff980000 FWH IDSEL: 0x2 0xffd00000/0xff900000 FWH IDSEL: 0x2 0xffc80000/0xff880000 FWH IDSEL: 0x3 0xffc00000/0xff800000 FWH IDSEL: 0x3 0xff700000/0xff300000 FWH IDSEL: 0x4 0xff600000/0xff200000 FWH IDSEL: 0x5 0xff500000/0xff100000 FWH IDSEL: 0x6 0xff400000/0xff000000 FWH IDSEL: 0x7 0xfff80000/0xffb80000 FWH decode enabled 0xfff00000/0xffb00000 FWH decode enabled 0xffe80000/0xffa80000 FWH decode enabled 0xffe00000/0xffa00000 FWH decode enabled 0xffd80000/0xff980000 FWH decode enabled 0xffd00000/0xff900000 FWH decode enabled 0xffc80000/0xff880000 FWH decode enabled 0xffc00000/0xff800000 FWH decode enabled 0xff700000/0xff300000 FWH decode enabled 0xff600000/0xff200000 FWH decode enabled 0xff500000/0xff100000 FWH decode enabled 0xff400000/0xff000000 FWH decode enabled BIOS Lock Enable: disabled, BIOS Write Enable: enabled, BIOS_CNTL is 0x1 Root Complex Register Block address = 0xfed1c000 GCS = 0x400500: BIOS Interface Lock-Down: disabled, BOOT BIOS Straps: 0x1 (SPI) Top Swap : not enabled SPIBAR = 0xfed1c000 + 0x3020 0x00: 0x0004 (SPIS) 0x02: 0x4130 (SPIC) 0x04: 0x00000000 (SPIA) 0x08: 0x00150000 (SPID0) 0x0c: 0x00000000 (SPID0+4) 0x10: 0x00000000 (SPID1) 0x14: 0x00000000 (SPID1+4) 0x18: 0x00000000 (SPID2) 0x1c: 0x00000000 (SPID2+4) 0x20: 0x00000000 (SPID3) 0x24: 0x00000000 (SPID3+4) 0x28: 0x00000000 (SPID4) 0x2c: 0x00000000 (SPID4+4) 0x30: 0x00000000 (SPID5) 0x34: 0x00000000 (SPID5+4) 0x38: 0x00ff80ea (SPID6) 0x3c: 0x2f3031f0 (SPID6+4) 0x40: 0x302f3531 (SPID7) 0x44: 0x05fc0039 (SPID7+4) 0x50: 0x00000000 (BBAR) 0x54: 0x0006 (PREOP) 0x56: 0x463b (OPTYPE) 0x58: 0x05d80302 (OPMENU) 0x5c: 0xc79f0190 (OPMENU+4) 0x60: 0x00000000 (PBR0) 0x64: 0x00000000 (PBR1) 0x68: 0x00000000 (PBR2) 0x6c: 0x00000000 (PBR3) Programming OPCODES... program_opcodes: preop=0006 optype=463b opmenu=05d80302c79f0190 done SPI Read Configuration: prefetching disabled, caching enabled, OK. This chipset supports the following protocols: SPI. Calibrating delay loop... 789M loops per second, 100 myus = 0 us. OK. Probing for Winbond W25x16, 2048 KB: RDID returned 0xef 0x30 0x15. probe_spi_rdid_generic: id1 0xef, id2 0x3015 Chip status register is 00 Found chip "Winbond W25x16" (2048 KB, SPI) at physical address 0xffe00000. === This flash part has status UNTESTED for operations: ERASE WRITE Please email a report to [email protected] if any of the above operations work correctly for you with this flash part. Please include the flashrom output with the additional -V option for all operations you tested (-V, -rV, -wV, -EV), and mention which mainboard you tested. Thanks for your help! === Flash image seems to be a legacy BIOS. Disabling checks. Writing flash chip... Programming page: opcode 0x06 will be run as PREOP ich_spi_write_page: offset=0, number=256, buf=0xb7896008 opcode 0x06 will be run as PREOP opcode 0x06 will be run as PREOP opcode 0x06 will be run as PREOP opcode 0x06 will be run as PREOP ich_spi_write_page: offset=256, number=256, buf=0xb7896108 opcode 0x06 will be run as PREOP opcode 0x06 will be run as PREOP opcode 0x06 will be run as PREOP opcode 0x06 will be run as PREOP ------------------------------------ the block "ich_spi.." and the four lines "opcode 0x06.." are replicated for every offset from 0 to 2096896, step 256 buf incremented by 0x100 ------------------------------------ ich_spi_write_page: offset=2096640, number=256, buf=0xb7a95e08 opcode 0x06 will be run as PREOP opcode 0x06 will be run as PREOP opcode 0x06 will be run as PREOP opcode 0x06 will be run as PREOP ich_spi_write_page: offset=2096896, number=256, buf=0xb7a95f08 opcode 0x06 will be run as PREOP opcode 0x06 will be run as PREOP opcode 0x06 will be run as PREOP opcode 0x06 will be run as PREOP COMPLETE. Verifying flash... VERIFIED.
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