Hi Anthony, On 07.01.2010 22:55, Anthony DeRosa wrote: > The bios version I am currently using (2.6.2) is no longer available for > download, but i happen to have a copy of it attached (raw ROM file).
I have stripped the ROM image from your mail before it could reach the list because we don't have distribution rights for ROM images. > Below is the rest of the info. you asked for. > > > ubu...@ubuntu:~/flashrom$ sudo ./flashrom -r backup.bin > flashrom v0.9.1-r837 > No coreboot table found. > Found chipset "Intel ICH8/ICH8R", enabling flash write... WARNING: SPI > Configuration Lockdown activated. > FAILED! > This chipset supports the following protocols: FWH,SPI. > Calibrating delay loop... OK. > Found chip "Macronix MX25L8005" (1024 KB, SPI) at physical address 0xfff00000. > Reading flash... done. > ubu...@ubuntu:~/flashrom$ hexdump backup.bin > 0000000 0000 0000 0000 0000 0000 0000 0000 0000 > * > 0100000 > Ouch. > dmidecode snippet (bonus!) > > Handle 0x0000, DMI type 0, 24 bytes > BIOS Information > Vendor: Dell Inc. > Version: 2.6.2 > ROM Size: 1024 kB > BIOS Revision: 2.6 > > > > > flashrom -V > > flashrom v0.9.1-r837 > No coreboot table found. > Found chipset "Intel ICH8/ICH8R", enabling flash write... > 0xfff80000/0xffb80000 FWH IDSEL: 0x0 > 0xfff00000/0xffb00000 FWH IDSEL: 0x0 > 0xffe80000/0xffa80000 FWH IDSEL: 0x1 > 0xffe00000/0xffa00000 FWH IDSEL: 0x1 > 0xffd80000/0xff980000 FWH IDSEL: 0x2 > 0xffd00000/0xff900000 FWH IDSEL: 0x2 > 0xffc80000/0xff880000 FWH IDSEL: 0x3 > 0xffc00000/0xff800000 FWH IDSEL: 0x3 > 0xff700000/0xff300000 FWH IDSEL: 0x4 > 0xff600000/0xff200000 FWH IDSEL: 0x5 > 0xff500000/0xff100000 FWH IDSEL: 0x6 > 0xff400000/0xff000000 FWH IDSEL: 0x7 > 0xfff80000/0xffb80000 FWH decode enabled > 0xfff00000/0xffb00000 FWH decode enabled > 0xffe80000/0xffa80000 FWH decode disabled > 0xffe00000/0xffa00000 FWH decode disabled > 0xffd80000/0xff980000 FWH decode disabled > 0xffd00000/0xff900000 FWH decode disabled > 0xffc80000/0xff880000 FWH decode disabled > 0xffc00000/0xff800000 FWH decode disabled > 0xff700000/0xff300000 FWH decode disabled > 0xff600000/0xff200000 FWH decode disabled > 0xff500000/0xff100000 FWH decode disabled > 0xff400000/0xff000000 FWH decode disabled > Maximum FWH chip size: 0x100000 bytes > BIOS Lock Enable: enabled, BIOS Write Enable: disabled, BIOS_CNTL is 0x2 > tried to set 0xdc to 0x3 on ICH8/ICH8R failed (WARNING ONLY) > OK, write to LPC flash is disabled. That's not good. > Root Complex Register Block address = 0xfeda8000 > GCS = 0x460: BIOS Interface Lock-Down: disabled, BOOT BIOS Straps: 0x1 (SPI) > Then again, your BIOS lives on SPI, so you do not care about LPC. > Top Swap : not enabled > SPIBAR = 0xfeda8000 + 0x3020 > 0x04: 0xa000 (HSFS) > FLOCKDN 1, FDV 0, FDOPSS 1, SCIP 0, BERASE 0, AEL 0, FCERR 0, FDONE 0 > FLOCKDN=1 is not that good and means we can't modify the opcodes in the chipset. FDV=0 is good. > 0x50: 0x00000202 (FRAP) > BMWAG 0, BMRAG 0, BRWA 2, BRRA 2 > 0x54: 0x00001fff (FREG0) > 0x58: 0x00001fff (FREG1) > 0x5C: 0x00001fff (FREG2) > 0x60: 0x00001fff (FREG3) > 0x64: 0x00000000 (FREG4) > Totally weird region configuration. > 0x74: 0x00000000 (PR0) > 0x78: 0x00000000 (PR1) > 0x7C: 0x00000000 (PR2) > 0x80: 0x00000000 (PR3) > 0x84: 0x00000000 (PR4) > 0x90: 0x00422004 (SSFS, SSFC) > 0x94: 0x0606 (PREOP) > 0x96: 0x4fc8 (OPTYPE) > 0x98: 0x029fabab (OPMENU) > 0x9C: 0x010502d8 (OPMENU+4) > 0xA0: 0x00000000 (BBAR) > 0xB0: 0x00000000 (FDOC) > WARNING: SPI Configuration Lockdown activated. > Good. flashrom detects the chipset lockdown. > Generating OPCODES... done > SPI Read Configuration: prefetching disabled, caching enabled, FAILED! > This chipset supports the following protocols: FWH,SPI. > Calibrating delay loop... 512M loops per second, 100 myus = 200 us. OK. > Probing for Macronix MX25L8005, 1024 KB: RDID returned 0xc2 0x20 0x14. > probe_spi_rdid_generic: id1 0xc2, id2 0x2014 > Chip status register is 00 > Chip status register: Status Register Write Disable (SRWD) is not set > Chip status register: Bit 6 is not set > Chip status register: Bit 5 / Block Protect 3 (BP3) is not set > Chip status register: Bit 4 / Block Protect 2 (BP2) is not set > Chip status register: Bit 3 / Block Protect 1 (BP1) is not set > Chip status register: Bit 2 / Block Protect 0 (BP0) is not set > Chip status register: Write Enable Latch (WEL) is not set > Chip status register: Write In Progress (WIP/BUSY) is not set > Found chip "Macronix MX25L8005" (1024 KB, SPI) at physical address 0xfff00000. > No operations were specified. > Hm. can you run flashrom -c MX25L8005 -V -r backup.bin and mail us about the output? There should be at least one transaction error or somesuch. We should NOT create a dump file on error. I have a patch for that in the queue. Regards, Carl-Daniel -- Developer quote of the year: "We are juggling too many chainsaws and flaming arrows and tigers." _______________________________________________ flashrom mailing list [email protected] http://www.flashrom.org/mailman/listinfo/flashrom
