On Sat, Jan 09, 2010 at 06:36:07PM +0100, [email protected] wrote:
> Author: mkarcher
> Date: 2010-01-09 18:36:06 +0100 (Sat, 09 Jan 2010)
> New Revision: 845
>
> Modified:
> trunk/board_enable.c
> Log:
> Enable flashing on MSI 651M-L.
>
> Signed-off-by: Michael Karcher <[email protected]>
> Acked-by: Sergey Lichack <[email protected]>
I seem unable to find the prerequisites for supporting this board on the
ml, lspci and superio.
The superio one is very important, as i need to know which superio this
is for the upcoming superio changes. I expect it to be a w83697(T)HF, as
so far only those required this memw enable (like the it8705 is the
only one require something rather similar).
But cool, we have our first sis gpio poker.
> +/**
> + * Enable some GPIO pin on SiS southbridge.
> + * Suited for MSI 651M-L: SiS651 / SiS962
> + */
> +static int board_msi_651ml(const char *name)
> +{
> + struct pci_dev *dev;
> + uint16_t base;
> + uint16_t temp;
> +
> + dev = pci_dev_find(0x1039, 0x0962);
> + if (!dev) {
> + fprintf(stderr, "Expected south bridge not found\n");
> + return 1;
> + }
> +
> + /* Registers 68 and 64 seem like bitmaps */
> + base = pci_read_word(dev, 0x74);
> + temp = INW(base + 0x68);
> + temp &= ~(1 << 0); /* Make pin output? */
> + printf_debug("changed to %04x\n",temp);
Where do you end up writing this bit?
> +
> + temp = INW(base + 0x64);
> + temp |= (1 << 0); /* Raise output? */
> + OUTW(temp, base + 0x64);
> +
> + w836xx_memw_enable(0x2E);
> +
> + return 0;
> +}
> +
One or two more of these routines, and we might make a first stab at a
general sis gpio routine.
Luc Verhaegen.
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