Hi,
Attached is a patch to board_enable.c for the HP DL165 board.
Apparently, the PCI signature of the DL165 is identical to the DL145,
but the enable pins are placed differently... :/ I'm not sure what the
best way to handle that is.
Signed-off-by: Arne Georg Gleditsch <[email protected]>
--
Arne.
Index: board_enable.c
===================================================================
--- board_enable.c (revision 1013)
+++ board_enable.c (working copy)
@@ -518,6 +518,15 @@
return 0;
}
+static int board_hp_dl165_g6_enable(const char *name)
+{
+ /* Variant of DL145, with slightly different pin placement. */
+ sio_mask(0xcd6, 0x44, 0x80, 0x80); /* TBL# */
+ sio_mask(0xcd6, 0x46, 0x04, 0x04); /* WP# */
+
+ return 0;
+}
+
static int board_ibm_x3455(const char *name)
{
/* raise gpio13 */
@@ -1435,6 +1444,7 @@
{0x1106, 0x3227, 0x1458, 0x5001, 0x10ec, 0x8139, 0x1458, 0xe000, NULL,
NULL, NULL, "GIGABYTE", "GA-7VT600",
0, OK, it8705f_write_enable_2e},
{0x10DE, 0x0050, 0x1458, 0x0C11, 0x10DE, 0x005e, 0x1458, 0x5000, NULL,
NULL, NULL, "GIGABYTE", "GA-K8N-SLI",
0, OK, nvidia_mcp_gpio21_raise},
{0x1166, 0x0223, 0x103c, 0x320d, 0x102b, 0x0522, 0x103c, 0x31fa, NULL,
"hp", "dl145_g3", "HP", "DL145 G3",
0, OK, board_hp_dl145_g3_enable},
+ {0x1166, 0x0223, 0x103c, 0x320d, 0x102b, 0x0522, 0x103c, 0x31fa, NULL,
"hp", "dl165_g6", "HP", "DL165 G6",
0, OK, board_hp_dl165_g6_enable},
{0x8086, 0x2415, 0x103c, 0x1249, 0x10b7, 0x9200, 0x103c, 0x1246, NULL,
NULL, NULL, "HP", "Vectra VL400",
0, OK, board_hp_vl400},
{0x8086, 0x1a30, 0x103c, 0x1a30, 0x8086, 0x2443, 0x103c, 0x2440,
"^VL420$", NULL, NULL, "HP", "VL420 SFF",
0, OK, intel_ich_gpio22_raise},
{0x8086, 0x27A0, 0, 0, 0x8086, 0x27B9, 0, 0, NULL,
"ibase", "mb899", "iBASE", "MB899",
0, NT, intel_ich_gpio26_raise},
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