On 28.05.2010 19:04, Stefan Reinauer wrote: > On 5/28/10 6:50 PM, Carl-Daniel Hailfinger wrote: > >> Some chips implement the RES (0xab) opcode, but they use a non-standard >> two byte response instead of the usual one byte response. >> A two-byte response has the accuracy of REMS and RDID, so don't check >> for REMS/RDID availability before running a two-byte RES. >> >> > Acked-by: Stefan Reinauer <[email protected]> >
Thanks, committed in r1017. > Found chipset "Intel ICH7/ICH7R", enabling flash write... > [...] > WARNING: SPI Configuration Lockdown activated. > FAILED! > This chipset supports the following protocols: SPI. > ich_spi_send_command: Address 0x000000 below allowed range 0xf80000-0xffffff > Found chip "SST SST25LF040A" (512 KB, SPI) at physical address 0xfff80000. > ich_spi_send_command: Address 0x000000 below allowed range 0xf80000-0xffffff > ich_spi_send_command: Address 0x000000 below allowed range 0xf80000-0xffffff > ich_spi_send_command: Address 0x000000 below allowed range 0xf80000-0xffffff > No operations were specified. > Very nice, thanks for the log. I expect reading/writing to fail because those commands don't care about the minim address yet. Regards, Carl-Daniel -- http://www.hailfinger.org/ _______________________________________________ flashrom mailing list [email protected] http://www.flashrom.org/mailman/listinfo/flashrom
