Hi Rudolf,
On Mon, 2010-07-12 at 20:37 +0200, Rudolf Marek wrote:
> Hi,
>
> I checked with those two PT and PU chips A25L40. I think they still report
> with
> your patch as same chip:
>
> With PT chip:
>
> robing for AMIC A25L05PT, 64 KB: probe_spi_rdid_generic: id1 0x7f37, id2
> 0x2013
> Probing for AMIC A25L05PU, 64 KB: probe_spi_rdid_generic: id1 0x7f37, id2
> 0x2013
> Probing for AMIC A25L10PT, 128 KB: probe_spi_rdid_generic: id1 0x7f37, id2
> 0x2013
> Probing for AMIC A25L10PU, 128 KB: probe_spi_rdid_generic: id1 0x7f37, id2
> 0x2013
> Probing for AMIC A25L20PT, 256 KB: probe_spi_rdid_generic: id1 0x7f37, id2
> 0x2013
> Probing for AMIC A25L20PU, 256 KB: probe_spi_rdid_generic: id1 0x7f37, id2
> 0x2013
> Probing for AMIC A25L40PT, 512 KB: probe_spi_rdid_generic: id1 0x7f37, id2
> 0x2013
> Probing for AMIC A25L40PU, 512 KB: probe_spi_rdid_generic: id1 0x7f37, id2
> 0x2013
> Chip status register is 00
> Chip status register: Status Register Write Disable (SRWD) is not set
> Chip status register: Bit 5 / Block Protect 3 (BP3) is not set
> Chip status register: Bit 4 / Block Protect 2 (BP2) is not set
> Chip status register: Bit 3 / Block Protect 1 (BP1) is not set
> Chip status register: Bit 2 / Block Protect 0 (BP0) is not set
> Chip status register: Write Enable Latch (WEL) is not set
> Chip status register: Write In Progress (WIP/BUSY) is not set
> Found chip "AMIC A25L40PU" (512 KB, SPI) at physical address 0xfff80000.
> Probing for AMIC A25L80P, 1024 KB: probe_spi_rdid_generic: id1 0x7f37, id2
> 0x2013
>
>
> with PU chip:
>
> Probing for AMIC A25L05PT, 64 KB: probe_spi_rdid_generic: id1 0x7f37, id2
> 0x2013
> Probing for AMIC A25L05PU, 64 KB: probe_spi_rdid_generic: id1 0x7f37, id2
> 0x2013
> Probing for AMIC A25L10PT, 128 KB: probe_spi_rdid_generic: id1 0x7f37, id2
> 0x2013
> Probing for AMIC A25L10PU, 128 KB: probe_spi_rdid_generic: id1 0x7f37, id2
> 0x2013
> Probing for AMIC A25L20PT, 256 KB: probe_spi_rdid_generic: id1 0x7f37, id2
> 0x2013
> Probing for AMIC A25L20PU, 256 KB: probe_spi_rdid_generic: id1 0x7f37, id2
> 0x2013
> Probing for AMIC A25L40PT, 512 KB: probe_spi_rdid_generic: id1 0x7f37, id2
> 0x2013
> Probing for AMIC A25L40PU, 512 KB: probe_spi_rdid_generic: id1 0x7f37, id2
> 0x2013
> Chip status register is 00
> Chip status register: Status Register Write Disable (SRWD) is not set
> Chip status register: Bit 5 / Block Protect 3 (BP3) is not set
> Chip status register: Bit 4 / Block Protect 2 (BP2) is not set
> Chip status register: Bit 3 / Block Protect 1 (BP1) is not set
> Chip status register: Bit 2 / Block Protect 0 (BP0) is not set
> Chip status register: Write Enable Latch (WEL) is not set
> Chip status register: Write In Progress (WIP/BUSY) is not set
> Found chip "AMIC A25L40PU" (512 KB, SPI) at physical address 0xfff80000.
> Probing for AMIC A25L80P, 1024 KB: probe_spi_rdid_generic: id1 0x7f37, id2
> 0x2013
> Probing for AMIC A29002B, 256 KB: skipped.
Very interesting... so they really do both report the same model_ID of
0x2013.
What happens if you try to selectively write or erase only the bottom 4
KB of each chip?
* If it works on the PU chip (bottom boot block) but fails on the
PT chip (top boot block), then it looks like their erase block
granularity is accurately described by the data sheet, although
there's no way to distinguish them by RDID.
* If it /works/ on both, then that suggests that the 40PT chip is
in fact /identical/ to the 40PU chip.
> Check attachment for full log. I had to delete AMIC A25L16 because it had some
> typo...
Sorry about that. Due to a mailer crash and my noob confusion, I ended
up sending two patches, one of which was functional, and one of which
was not. The correct, complete patch is attached to this message, but
it should not be applied yet if the 40PU and 40PT chips really do turn
out to be distinct parts with the same RDID.
Dan
Index: spi25.c
===================================================================
--- spi25.c (revision 1075)
+++ spi25.c (working copy)
@@ -328,6 +328,16 @@
}
/* Prettyprint the status register. Works for
+ * AMIC A25L series
+ */
+void spi_prettyprint_status_register_amic_a25l(uint8_t status)
+{
+ msg_cdbg("Chip status register: Status Register Write Disable "
+ "(SRWD) is %sset\n", (status & (1 << 7)) ? "" : "not ");
+ spi_prettyprint_status_register_common(status);
+}
+
+/* Prettyprint the status register. Works for
* ST M25P series
* MX MX25L series
*/
@@ -389,6 +399,10 @@
status = spi_read_status_register();
msg_cdbg("Chip status register is %02x\n", status);
switch (flash->manufacture_id) {
+ case AMIC_ID:
+ if ((flash->model_id & 0xff00) == 0x2000)
+ spi_prettyprint_status_register_amic_a25l(status);
+ break;
case ST_ID:
if (((flash->model_id & 0xff00) == 0x2000) ||
((flash->model_id & 0xff00) == 0x2500))
Index: flashchips.c
===================================================================
--- flashchips.c (revision 1075)
+++ flashchips.c (working copy)
@@ -1155,14 +1155,206 @@
.read = read_memmapped,
},
- /* The next two chip definitions have top/bottom boot blocks, but has no
- device differentiation between the two */
+ /* AMIC */
+
{
.vendor = "AMIC",
+ .name = "A25L05PT",
+ .bustype = CHIP_BUSTYPE_SPI,
+ .manufacture_id = AMIC_ID,
+ .model_id = AMIC_A25L05PT,
+ .total_size = 64,
+ .page_size = 256,
+ .tested = TEST_UNTESTED,
+ .probe = probe_spi_rdid4,
+ .probe_timing = TIMING_ZERO,
+ .block_erasers =
+ {
+ {
+ .eraseblocks = {
+ {32 * 1024, 1},
+ {16 * 1024, 1},
+ {8 * 1024, 1},
+ {4 * 1024, 2},
+ },
+ .block_erase = spi_block_erase_d8,
+ }, {
+ .eraseblocks = { {64 * 1024, 1} },
+ .block_erase = spi_block_erase_c7,
+ }
+ },
+ .write = spi_chip_write_256,
+ .read = spi_chip_read,
+ },
+
+ {
+ .vendor = "AMIC",
+ .name = "A25L05PU",
+ .bustype = CHIP_BUSTYPE_SPI,
+ .manufacture_id = AMIC_ID,
+ .model_id = AMIC_A25L05PU,
+ .total_size = 64,
+ .page_size = 256,
+ .tested = TEST_UNTESTED,
+ .probe = probe_spi_rdid4,
+ .probe_timing = TIMING_ZERO,
+ .block_erasers =
+ {
+ {
+ .eraseblocks = {
+ {4 * 1024, 2},
+ {8 * 1024, 1},
+ {16 * 1024, 1},
+ {32 * 1024, 1},
+ },
+ .block_erase = spi_block_erase_d8,
+ }, {
+ .eraseblocks = { {64 * 1024, 1} },
+ .block_erase = spi_block_erase_c7,
+ }
+ },
+ .write = spi_chip_write_256,
+ .read = spi_chip_read,
+ },
+
+ {
+ .vendor = "AMIC",
+ .name = "A25L10PT",
+ .bustype = CHIP_BUSTYPE_SPI,
+ .manufacture_id = AMIC_ID,
+ .model_id = AMIC_A25L10PT,
+ .total_size = 128,
+ .page_size = 256,
+ .tested = TEST_UNTESTED,
+ .probe = probe_spi_rdid4,
+ .probe_timing = TIMING_ZERO,
+ .block_erasers =
+ {
+ {
+ .eraseblocks = {
+ {64 * 1024, 1},
+ {32 * 1024, 1},
+ {16 * 1024, 1},
+ {8 * 1024, 1},
+ {4 * 1024, 2},
+ },
+ .block_erase = spi_block_erase_d8,
+ }, {
+ .eraseblocks = { {128 * 1024, 1} },
+ .block_erase = spi_block_erase_c7,
+ }
+ },
+ .write = spi_chip_write_256,
+ .read = spi_chip_read,
+ },
+
+ {
+ .vendor = "AMIC",
+ .name = "A25L10PU",
+ .bustype = CHIP_BUSTYPE_SPI,
+ .manufacture_id = AMIC_ID,
+ .model_id = AMIC_A25L10PU,
+ .total_size = 128,
+ .page_size = 256,
+ .tested = TEST_UNTESTED,
+ .probe = probe_spi_rdid4,
+ .probe_timing = TIMING_ZERO,
+ .block_erasers =
+ {
+ {
+ .eraseblocks = {
+ {4 * 1024, 2},
+ {8 * 1024, 1},
+ {16 * 1024, 1},
+ {32 * 1024, 1},
+ {64 * 1024, 1},
+ },
+ .block_erase = spi_block_erase_d8,
+ }, {
+ .eraseblocks = { {128 * 1024, 1} },
+ .block_erase = spi_block_erase_c7,
+ }
+ },
+ .write = spi_chip_write_256,
+ .read = spi_chip_read,
+ },
+
+ {
+ .vendor = "AMIC",
+ .name = "A25L20PT",
+ .bustype = CHIP_BUSTYPE_SPI,
+ .manufacture_id = AMIC_ID,
+ .model_id = AMIC_A25L20PT,
+ .total_size = 256,
+ .page_size = 256,
+ .tested = TEST_UNTESTED,
+ .probe = probe_spi_rdid4,
+ .probe_timing = TIMING_ZERO,
+ .block_erasers =
+ {
+ {
+ .eraseblocks = {
+ {64 * 1024, 3},
+ {32 * 1024, 1},
+ {16 * 1024, 1},
+ {8 * 1024, 1},
+ {4 * 1024, 2},
+ },
+ .block_erase = spi_block_erase_d8,
+ }, {
+ .eraseblocks = { {256 * 1024, 1} },
+ .block_erase = spi_block_erase_c7,
+ }
+ },
+ .write = spi_chip_write_256,
+ .read = spi_chip_read,
+ },
+
+ {
+ .vendor = "AMIC",
+ .name = "A25L20PU",
+ .bustype = CHIP_BUSTYPE_SPI,
+ .manufacture_id = AMIC_ID,
+ .model_id = AMIC_A25L20PU,
+ .total_size = 256,
+ .page_size = 256,
+ .tested = TEST_UNTESTED,
+ .probe = probe_spi_rdid4,
+ .probe_timing = TIMING_ZERO,
+ .block_erasers =
+ {
+ {
+ .eraseblocks = {
+ {4 * 1024, 2},
+ {8 * 1024, 1},
+ {16 * 1024, 1},
+ {32 * 1024, 1},
+ {64 * 1024, 3},
+ },
+ .block_erase = spi_block_erase_d8,
+ }, {
+ .eraseblocks = { {256 * 1024, 1} },
+ .block_erase = spi_block_erase_c7,
+ }
+ },
+ .write = spi_chip_write_256,
+ .read = spi_chip_read,
+ },
+
+ /* The entries for A25L40P{T,U} previously distinguished
+ * top/bottom boot blocks, without any distinction in RDID.
+ * This is probably an error in the datasheets from AMIC,
+ * since the A25L{05,10,20,16}{T/U} parts all distinguish
+ * top/bottom boot blocks in the RDID. I've changed the
+ * model_ID for A25L40PT to reflect what it "should" be
+ * according to the established pattern.
+ */
+ {
+ .vendor = "AMIC",
.name = "A25L40PT",
.bustype = CHIP_BUSTYPE_SPI,
.manufacture_id = AMIC_ID,
- .model_id = AMIC_A25L40P,
+ .model_id = AMIC_A25L40PT,
.total_size = 512,
.page_size = 256,
.tested = TEST_OK_PRW,
@@ -1193,7 +1385,7 @@
.name = "A25L40PU",
.bustype = CHIP_BUSTYPE_SPI,
.manufacture_id = AMIC_ID,
- .model_id = AMIC_A25L40P,
+ .model_id = AMIC_A25L40PU,
.total_size = 512,
.page_size = 256,
.tested = TEST_OK_PRW,
@@ -1252,6 +1444,68 @@
{
.vendor = "AMIC",
+ .name = "A25L16PT",
+ .bustype = CHIP_BUSTYPE_SPI,
+ .manufacture_id = AMIC_ID,
+ .model_id = AMIC_A25L16PT,
+ .total_size = 2048,
+ .page_size = 256,
+ .tested = TEST_UNTESTED,
+ .probe = probe_spi_rdid4,
+ .probe_timing = TIMING_ZERO,
+ .block_erasers =
+ {
+ {
+ .eraseblocks = {
+ {64 * 1024, 31},
+ {32 * 1024, 1},
+ {16 * 1024, 1},
+ {8 * 1024, 1},
+ {4 * 1024, 2},
+ },
+ .block_erase = spi_block_erase_d8,
+ }, {
+ .eraseblocks = { {2048 * 1024, 1} },
+ .block_erase = spi_block_erase_c7,
+ }
+ },
+ .write = spi_chip_write_256,
+ .read = spi_chip_read,
+ },
+
+ {
+ .vendor = "AMIC",
+ .name = "A25L16PU",
+ .bustype = CHIP_BUSTYPE_SPI,
+ .manufacture_id = AMIC_ID,
+ .model_id = AMIC_A25L16PU,
+ .total_size = 2048,
+ .page_size = 256,
+ .tested = TEST_OK_PRW,
+ .probe = probe_spi_rdid4,
+ .probe_timing = TIMING_ZERO,
+ .block_erasers =
+ {
+ {
+ .eraseblocks = {
+ {4 * 1024, 2},
+ {8 * 1024, 1},
+ {16 * 1024, 1},
+ {32 * 1024, 1},
+ {64 * 1024, 31},
+ },
+ .block_erase = spi_block_erase_d8,
+ }, {
+ .eraseblocks = { { 2048 * 1024, 1 } },
+ .block_erase = spi_block_erase_c7,
+ }
+ },
+ .write = spi_chip_write_256,
+ .read = spi_chip_read,
+ },
+
+ {
+ .vendor = "AMIC",
.name = "A29002B",
.bustype = CHIP_BUSTYPE_PARALLEL,
.manufacture_id = AMIC_ID_NOPREFIX,
@@ -6491,7 +6745,23 @@
.read = read_memmapped,
},
+ /* generic SPI chips */
{
+ .vendor = "AMIC",
+ .name = "unknown AMIC SPI chip",
+ .bustype = CHIP_BUSTYPE_SPI,
+ .manufacture_id = AMIC_ID,
+ .model_id = GENERIC_DEVICE_ID,
+ .total_size = 0,
+ .page_size = 256,
+ .tested = TEST_BAD_PREW,
+ .probe = probe_spi_rdid4,
+ .probe_timing = TIMING_ZERO,
+ .write = NULL,
+ .read = NULL,
+ },
+
+ {
.vendor = "Atmel",
.name = "unknown Atmel SPI chip",
.bustype = CHIP_BUSTYPE_SPI,
Index: flashchips.h
===================================================================
--- flashchips.h (revision 1075)
+++ flashchips.h (working copy)
@@ -75,8 +75,20 @@
#define AMIC_ID 0x7F37 /* AMIC */
#define AMIC_ID_NOPREFIX 0x37 /* AMIC */
-#define AMIC_A25L40P 0x2013
-#define AMIC_A25L80P 0x2014
+#define AMIC_A25L05PT 0x2020
+#define AMIC_A25L05PU 0x2010
+#define AMIC_A25L10PT 0x2021
+#define AMIC_A25L10PU 0x2011
+#define AMIC_A25L20PT 0x2022
+#define AMIC_A25L20PU 0x2012
+#define AMIC_A25L40PT 0x2023 /* Datasheet says T and U have
+ same device ID, but this
+ seems implausible given the
+ clear pattern */
+#define AMIC_A25L40PU 0x2013
+#define AMIC_A25L80P 0x2014 /* Seems that no A25L80PT exists */
+#define AMIC_A25L16PT 0x2025
+#define AMIC_A25L16PU 0x2015
#define AMIC_A29002B 0x0d
#define AMIC_A29002T 0x8C /* Same as A290021T */
#define AMIC_A29040B 0x86
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