Index: board_enable.c
===================================================================
--- board_enable.c	(revision 1138)
+++ board_enable.c	(working copy)
@@ -996,6 +996,44 @@
 	struct pci_dev *dev;
 	uint32_t tmp, base;
 
+	static const uint32_t forbidden_gpos = 0x00000100; /* GPO8 is never available */
+	static const uint32_t nonmuxed_gpos  = 0x58000001; /* GPPO {0,27,28,30} are always available */
+
+	static const struct {unsigned int reg, mask, value; } piix4_gpo[] = {
+	  {0},
+	  {0xB0, 0x0001, 0x0000},        /* GPO1... */
+	  {0xB0, 0x0001, 0x0000},
+	  {0xB0, 0x0001, 0x0000},
+	  {0xB0, 0x0001, 0x0000},
+	  {0xB0, 0x0001, 0x0000},
+	  {0xB0, 0x0001, 0x0000},
+	  {0xB0, 0x0001, 0x0000},        /* ...GPO7: GENCFG bit 0 */
+	  {0},
+	  {0xB0, 0x0100, 0x0000},        /* GPO9:  GENCFG bit 8 */
+	  {0xB0, 0x0200, 0x0000},        /* GPO10: GENCFG bit 9 */
+	  {0xB0, 0x0400, 0x0000},        /* GPO11: GENCFG bit 10 */
+	  {0x4E, 0x0100, 0x0000},        /* GPO12... */
+	  {0x4E, 0x0100, 0x0000},
+	  {0x4E, 0x0100, 0x0000},        /* ...GPO14: XBCS bit 8 */
+	  {0xB2, 0x0002, 0x0002},        /* GPO15... */
+	  {0xB2, 0x0002, 0x0002},        /* ...GPO16: GENCFG bit 17 */
+	  {0xB2, 0x0004, 0x0004},        /* GPO17: GENCFG bit 18 */
+	  {0xB2, 0x0008, 0x0008},        /* GPO18: GENCFG bit 19 */
+	  {0xB2, 0x0010, 0x0010},        /* GPO19: GENCFG bit 20 */
+	  {0xB2, 0x0020, 0x0020},        /* GPO20: GENCFG bit 21 */
+	  {0xB2, 0x0040, 0x0040},        /* GPO21: GENCFG bit 22 */
+	  {0xB2, 0x1000, 0x1000},        /* GPO22... */
+	  {0xB2, 0x1000, 0x1000},        /* ...GPO23: GENCFG bit 28 */
+	  {0xB2, 0x2000, 0x2000},        /* GPO24: GENCFG bit 29 */
+	  {0xB2, 0x4000, 0x4000},        /* GPO25: GENCFG bit 30 */
+	  {0xB2, 0x8000, 0x8000},        /* GPO26: GENCFG bit 31 */
+	  {0},
+	  {0},
+	  {0x4E, 0x0100, 0x0000},        /* ...GPO29: XBCS bit 8 */
+	  {0}
+	};
+
+
 	dev = pci_dev_find(0x8086, 0x7110);	/* Intel PIIX4 ISA bridge */
 	if (!dev) {
 		msg_perr("\nERROR: Intel PIIX4 ISA bridge not found.\n");
@@ -1008,36 +1046,17 @@
 		return -1;
 	}
 
-	/* These are dual function pins which are most likely in use already. */
-	if (((gpo >= 1) && (gpo <= 7)) ||
-	    ((gpo >= 9) && (gpo <= 21)) || (gpo == 29)) {
-		msg_perr("\nERROR: Unsupported PIIX4 GPO%d.\n", gpo);
-		return -1;
+	if (((1 << gpo) & forbidden_gpos)) {
+	  msg_perr("\nERROR: Forbidden PIIX4 GPO%d.\n", gpo);
+	  return -1;
 	}
 
-	/* Dual function that need special enable. */
-	if ((gpo >= 22) && (gpo <= 26)) {
-		tmp = pci_read_long(dev, 0xB0); /* GENCFG */
-		switch (gpo) {
-		case 22: /* XBUS: XDIR#/GPO22 */
-		case 23: /* XBUS: XOE#/GPO23 */
-			tmp |= 1 << 28;
-			break;
-		case 24: /* RTCSS#/GPO24 */
-			tmp |= 1 << 29;
-			break;
-		case 25: /* RTCALE/GPO25 */
-			tmp |= 1 << 30;
-			break;
-		case 26: /* KBCSS#/GPO26 */
-			tmp |= 1 << 31;
-			break;
-		}
-		pci_write_long(dev, 0xB0, tmp);
+	if ( (((1 << gpo) & nonmuxed_gpos) == 0) &&
+	     (pci_read_word(dev, piix4_gpo[gpo].reg) & piix4_gpo[gpo].mask) != piix4_gpo[gpo].value ) {
+	  msg_perr("\nERROR: PIIX4 GPO\%d not programmed for output.\n", gpo);
+	  return -1;
 	}
 
-	/* GPO {0,8,27,28,30} are always available. */
-
 	dev = pci_dev_find(0x8086, 0x7113);	/* Intel PIIX4 PM */
 	if (!dev) {
 		msg_perr("\nERROR: Intel PIIX4 PM not found.\n");