On 15.09.2010 11:10, Joshua Roys wrote: > Attached is a patch that might get your flash chip to appear- a > chipset enable was put into place, and some flash chips were added > that could have been used in your board. It's possible but unlikely > that write would work, mostly due to the following: > > On Tue, Sep 14, 2010 at 7:33 AM, Carl-Daniel Hailfinger > <[email protected]> wrote: > >> OK. The board has a "JP1 firmware write protect" jumper, so writing >> would probably be impossible without opening the case. >> It _is_ possible that this jumper also prevents probing, but I'm not so >> sure about that. >> > > Apply the patch on the latest SVN. Depending on when you try to > apply, it might need some changes. (The diff was generated on r1171.) > > --- a/chipset_enable.c > +++ b/chipset_enable.c > @@ -802,6 +802,23 @@ static int enable_flash_ck804(struct pci_dev *dev, const > char *name) > return 0; > } > > +static int enable_flash_osb4(struct pci_dev *dev, const char *name) > +{ > + uint8_t tmp; > + > + buses_supported = CHIP_BUSTYPE_PARALLEL; > + > + tmp = INB(0xc06); > + tmp |= 0x1; > + OUTB(tmp, 0xc06); > + > + tmp = INB(0xc6f); > + tmp |= 0x40; > + OUTB(tmp, 0xc6f); > + > + return 0; > +} > + >
Funny. The 0xc6f access looks very similar to parts of the SB400 chipset enable. (Side note: we should ask AMD if the SB400 chipset enable is correct.) Peter, could you please attach /proc/ioports and check if dmesg mentions 0xc06 or 0xc6f or anything close to that? Joshua, I would like this in 0.9.3. Would it be OK for you to split the patch in a chipset enable and a flash chip addition? If possible, coordinate with Mattias to avoid conflicts in flashchips.[ch] Regards, Carl-Daniel -- http://www.hailfinger.org/ _______________________________________________ flashrom mailing list [email protected] http://www.flashrom.org/mailman/listinfo/flashrom
