localhost2 bios # flashrom -w /home/roger/src/coreboot-tyan_s1832dl/coreboot/build/coreboot.rom flashrom v0.9.3-r1205 on Linux 2.6.37-gentoo (i686), built with libpci 3.1.4, GCC 4.4.4, little endian flashrom is free software, get the source code at http://www.flashrom.org
Calibrating delay loop... OK. No coreboot table found. Found chipset "Intel PIIX4/4E/4M", enabling flash write... OK. This chipset supports the following protocols: Parallel. Found chip "SST SST39SF040" (512 KB, Parallel) at physical address 0xfff80000. Note: If the following flash access fails, try -m <vendor>:<mainboard>. Writing flash chip... Erasing flash chip... SUCCESS. Programming page: DONE!ss: 0x0007f000 COMPLETE. Verifying flash... VERIFY FAILED at 0x0003fc9e! Expected=0xff, Read=0x4f, failed byte count from 0x00000000-0x0007ffff: 0x231f7 Your flash chip is in an unknown state. Get help on IRC at irc.freenode.net (channel #flashrom) or mail [email protected] with FAILED: your board name in the subject line! ------------------------------------------------------------------------------- DO NOT REBOOT OR POWEROFF! DIGI-KEY Part No. SST39SF040-70-4C-PHE IC FLASH MPF 4MBIT (512KBYTES) 70NS 32DIP This is flashing using a Tyan S1832DL board 00:00.0 Host bridge: Intel Corporation 440BX/ZX/DX - 82443BX/ZX/DX Host bridge (rev 03) ... 00:07.0 ISA bridge: Intel Corporation 82371AB/EB/MB PIIX4 ISA (rev 02) (... am I getting this right, flashrom uses the ISA bridge to write to flash part?) -- Roger http://rogerx.freeshell.org/ _______________________________________________ flashrom mailing list [email protected] http://www.flashrom.org/mailman/listinfo/flashrom
