Hello, This is for csugah from IRC. http://paste.flashrom.org/view.php?id=570 http://paste.flashrom.org/view.php?id=571 http://paste.flashrom.org/view.php?id=572 http://paste.flashrom.org/view.php?id=573
The attached patch should help diagnose your board. Also, csugah, try this patch to fix the segv you were seeing:
http://patchwork.coreboot.org/patch/2878/ Add lock printing for the AMD8111. Signed-off-by: Joshua Roys <[email protected]> Joshua Roys
>From 0c37f46b4637548781314aff344a133f44e23af4 Mon Sep 17 00:00:00 2001 From: Joshua Roys <[email protected]> Date: Mon, 16 May 2011 14:55:52 -0400 Subject: [PATCH] Add lock printing for the AMD8111 There are 25 OAR (open at reset) locks on the AMD8111 covering different ranges of the possible BIOS memory. This patch attempts to show chip-relative addresses if the range falls within the chip, and absolute addresses otherwise. Signed-off-by: Joshua Roys <[email protected]> --- chipset_enable.c | 52 ++++++++++++++++++++++++++++++++++++++++++++++++++++ 1 files changed, 52 insertions(+), 0 deletions(-) diff --git a/chipset_enable.c b/chipset_enable.c index 8b6b71c..7f2b60b 100644 --- a/chipset_enable.c +++ b/chipset_enable.c @@ -649,11 +649,63 @@ static int enable_flash_sc1100(struct pci_dev *dev, const char *name) return 0; } +static void print_amd8111_oar(uint8_t regnum, uint32_t base, uint32_t range, uint8_t oar) +{ + static const char *const oar_rw_bits[4] = { + "Read-Write", + "Write-Only", + "Read-Only", + "No access" + }; + static const char *const oar_lock_bits[4] = { + "locks modifiable", + "locks modifiable in SMM", + "locked", + "locked" + }; + + msg_pdbg("OAR%X: (0x%08x-0x%08x) %s, %s\n", + regnum, + flashbase && base >= flashbase ? (uint32_t)(base - flashbase) : base, + flashbase && base >= flashbase ? (uint32_t)(base - flashbase + range - 1) : base + range - 1, + oar_rw_bits[oar & 0x03], + oar_lock_bits[(oar >> 2) & 0x03] + ); +} + +static void print_amd8111_locks(struct pci_dev *dev) +{ + uint8_t i, oar_control; + uint64_t oar_fff0; + uint32_t oar80, oar84, oar_ffbf; + + oar80 = pci_read_long(dev, 0x80); + oar84 = pci_read_long(dev, 0x84); + oar_fff0 = (((uint64_t)oar84 << 32) | oar80); + oar_ffbf = pci_read_long(dev, 0x88); + oar_control = pci_read_byte(dev, 0x8c); + + msg_pdbg("0x80: 0x%08x (OAR lock high 0-7)\n", oar80); + msg_pdbg("0x84: 0x%08x (OAR lock high 8-F)\n", oar84); + msg_pdbg("0x88: 0x%08x (OAR lock low)\n", oar_ffbf); + msg_pdbg("0x8C: 0x%02x (OAR control register)\n", oar_control); + + for(i = 0; i < 16; i++) { + print_amd8111_oar(i, 0xfff00000 | (i << 16), (1 << 16), (uint8_t)((oar_fff0 >> (i * 4)) & 0x0f)); + } + for(i = 0; i < 8; i++) { + print_amd8111_oar(i * 2, 0xffbf0000 | (i << 13), (1 << 13), (uint8_t)((oar_ffbf >> (i * 4)) & 0x0f)); + } + print_amd8111_oar(0, 0xffc00000, (3 << 20), oar_control); +} + /* Works for AMD-8111, VIA VT82C586A/B, VIA VT82C686A/B. */ static int enable_flash_amd8111(struct pci_dev *dev, const char *name) { uint8_t old, new; + print_amd8111_locks(dev); + /* Enable decoding at 0xffb00000 to 0xffffffff. */ old = pci_read_byte(dev, 0x43); new = old | 0xC0; -- 1.7.3.4
_______________________________________________ flashrom mailing list [email protected] http://www.flashrom.org/mailman/listinfo/flashrom
