hello clr! you have missed carl-daniel or vice-versa one time and you never came back after that. i have dug up some info about the predecessor of your board i.e. 8NPA7I. the board enable that was executed on your machine by mistake is not complete (not even for the 8NPA7I) so it is expected to not work for you. i have not reverse engineered your bios (update tool), so i am not sure at all that the attached patch would help and not reboot/ruin/ignite your machine. but if you are brave you can try it.
PS: this patch is not for merge, because we have no idea what 0x92 really does imho. but we could incorporate this into a board enable function, if it really works or do you (fellow flashrom dev) think it is ok to just merge it as is? PPS: this is just a port of http://patchwork.coreboot.org/patch/2125/ -- Kind regards/Mit freundlichen Grüßen, Stefan Tauner
>From aae3e628dc499833f575594a6769d842ae2226b1 Mon Sep 17 00:00:00 2001 From: Stefan Tauner <[email protected]> Date: Sun, 19 Jun 2011 23:43:38 +0200 Subject: [PATCH] clear byte 0x92 of the LPC bridge for all CK804 chips The OEM BIOS on the EPoX EP-8PA7I clears byte 0x92 in the LPC bridge configuration space. Do the same for all CK804 chips, assuming this to be some sort of chipset-generic write-enable. Signed-off-by: Jonathan Kollasch <jakllsch at kollasch.net> --- chipset_enable.c | 5 +++++ 1 files changed, 5 insertions(+), 0 deletions(-) diff --git a/chipset_enable.c b/chipset_enable.c index 0c77f07..748b93e 100644 --- a/chipset_enable.c +++ b/chipset_enable.c @@ -775,6 +775,11 @@ static int enable_flash_ck804(struct pci_dev *dev, const char *name) { uint8_t old, new; + pci_write_byte(dev, 0x92, 0x00); + if (pci_read_byte(dev, 0x92) != 0x00) { + msg_pinfo("tried to set 0x%x to 0x%x on %s failed (WARNING ONLY)\n", 0x92, 0x00, name); + } + old = pci_read_byte(dev, 0x88); new = old | 0xc0; if (new != old) { -- 1.7.1
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