- add Asus Crosshair IV Extreme to the list of supported boards http://www.flashrom.org/pipermail/flashrom/2011-August/007640.html - add P7H55-M LX to the list of supported boards although flashrom works correctly, it is marked as not ok, because flashing the vendor image will break the LAN interface. - add GA-X58A-UD7 to the list of supported boards http://paste.flashrom.org/view.php?id=739 - add Asus P4P800-VM to print.c (has a working board enable) - add Asus K8V-X to print.c reported by florz http://paste.flashrom.org/view.php?id=742 - add Intel D865GLC to print.c reported by jmd on IRC http://paste.flashrom.org/view.php?id=775 - add ECS P4M800PRO-M (V1.0A) to the list of supported boards reported by dweg on IRC (hot flashed a SST49LF040B, original was W39V040B) - add X8DTU-6TF+ to print.c (needs ME unlocking) http://www.flashrom.org/pipermail/flashrom/2011-August/007553.html - add Shuttle FH67 (used in the SH67H3 barebone) to the list of supported boards http://www.flashrom.org/pipermail/flashrom/2011-August/007749.html - add Tyan S2912 to the list of supported boards reported by erlan on IRC - add Zotac GeForce 8200 to the list of supported boards http://www.flashrom.org/pipermail/flashrom/2011-August/007612.html
- mark AT25DF321A as TEST_OK_PROBE http://www.flashrom.org/pipermail/flashrom/2011-August/007553.html - mark 28F001BN/BX-T as TEST_OK_PR http://www.flashrom.org/pipermail/flashrom/2011-July/007208.html - rename MX29F002 http://patchwork.coreboot.org/patch/2794/ - mark SST39SF040 as fully tested reported by Florian 'florz' Zumbiehl http://paste.flashrom.org/view.php?id=742 - mark SST49LF040B as fully tested reported by dweg on IRC and later by Armin on the ml: http://www.flashrom.org/pipermail/flashrom/2011-August/007764.html - mark H55 chipset as OK http://www.flashrom.org/pipermail/flashrom/2011-July/007432.html - mark H67 chipset as OK http://www.flashrom.org/pipermail/flashrom/2011-August/007749.html - add preliminary X79 (patsburg) PCI IDs 0x1d40 was reported already as working (not archived in our pipermail?) - mark "82557/8/9/0/1 Ethernet Pro 100" in nicintel.c as working http://www.flashrom.org/pipermail/flashrom/2011-August/007480.html - rename some chips that had gratuitous "probing" suffixes: - SST25VF010.REMS - SST25VF040.REMS - M25P05.RES - M25P10.RES - remove unneeded nicintel_spi-related function declarations in programmer.h - typos and whitespace fixes - fix Asus P4P800-E Deluxe detection The original board enable was added before DMI matching and used the IDs of a Promise controller as secondary PCI ID set. The controller could be disabled in the BIOS which would make the board not match. This patch uses the SMBUS controller instead and adds a DMI pattern. This was Tested-by: Michael Schneider <vdrportal_midas at gmx dot de> - add "Sealed-case PC" to the list of chassis type (as indicating "not a laptop") This is Acked-by: Idwer Vollering <[email protected]> the fix for the typo unusued -> unused is Signed-off-by: Sylvain "ythier" Hitier <[email protected]> everything else is Signed-off-by: Stefan Tauner <[email protected]> Acked-by: Stefan Tauner <[email protected]> --- I think this is (more than) big enough to be committed. If no one vetoes i will commit it friday evening. board_enable.c | 2 +- chipset_enable.c | 12 +++++++----- dmi.c | 1 + flashchips.c | 24 ++++++++++++------------ flashchips.h | 8 ++++---- nicintel.c | 2 +- print.c | 11 +++++++++++ programmer.h | 3 --- 8 files changed, 37 insertions(+), 26 deletions(-) diff --git a/board_enable.c b/board_enable.c index 72f4cfe..896ab40 100644 --- a/board_enable.c +++ b/board_enable.c @@ -2018,7 +2018,7 @@ const struct board_pciid_enable board_pciid_enables[] = { {0x8086, 0x1A30, 0x1043, 0x8088, 0x8086, 0x24C3, 0x1043, 0x8089, NULL, NULL, NULL, P3, "ASUS", "P4B533-E", 0, NT, intel_ich_gpio22_raise}, {0x8086, 0x24D3, 0x1043, 0x80A6, 0x8086, 0x2578, 0x1043, 0x80F6, NULL, NULL, NULL, P3, "ASUS", "P4C800-E Deluxe", 0, OK, intel_ich_gpio21_raise}, {0x8086, 0x2570, 0x1043, 0x80F2, 0x8086, 0x24D5, 0x1043, 0x80F3, NULL, NULL, NULL, P3, "ASUS", "P4P800", 0, NT, intel_ich_gpio21_raise}, - {0x8086, 0x2570, 0x1043, 0x80F2, 0x105A, 0x3373, 0x1043, 0x80F5, NULL, NULL, NULL, P3, "ASUS", "P4P800-E Deluxe", 0, OK, intel_ich_gpio21_raise}, + {0x8086, 0x2570, 0x1043, 0x80F2, 0x8086, 0x24D3, 0x1043, 0x80A6, "^P4P800-E$", NULL, NULL, P3, "ASUS", "P4P800-E Deluxe", 0, OK, intel_ich_gpio21_raise}, {0x8086, 0x2570, 0x1043, 0x80A5, 0x8086, 0x24d0, 0, 0, NULL, NULL, NULL, P3, "ASUS", "P4P800-VM", 0, OK, intel_ich_gpio21_raise}, {0x1039, 0x0651, 0x1043, 0x8081, 0x1039, 0x0962, 0, 0, NULL, NULL, NULL, P3, "ASUS", "P4SC-E", 0, OK, it8707f_write_enable_2e}, {0x8086, 0x2570, 0x1043, 0x80A5, 0x105A, 0x24D3, 0x1043, 0x80A6, NULL, NULL, NULL, P3, "ASUS", "P4SD-LA", 0, NT, intel_ich_gpio32_raise}, diff --git a/chipset_enable.c b/chipset_enable.c index 336ad2e..ce00324 100644 --- a/chipset_enable.c +++ b/chipset_enable.c @@ -327,7 +327,7 @@ static int enable_flash_ich_dc(struct pci_dev *dev, const char *name) } if (fwh_idsel & 0xffff000000000000ULL) { msg_perr("Error: fwh_idsel= specified, but value had " - "unusued bits set.\n"); + "unused bits set.\n"); goto idsel_garbage_out; } fwh_idsel_old = pci_read_long(dev, 0xd0); @@ -341,7 +341,7 @@ static int enable_flash_ich_dc(struct pci_dev *dev, const char *name) /* FIXME: Decode settings are not changed. */ } else if (idsel) { msg_perr("Error: fwh_idsel= specified, but no value given.\n"); -idsel_garbage_out: +idsel_garbage_out: free(idsel); /* FIXME: Return failure here once internal_init() starts * to care about the return value of the chipset enable. @@ -846,7 +846,7 @@ static int enable_flash_ck804(struct pci_dev *dev, const char *name) if (new != old) { rpci_write_byte(dev, 0x88, new); if (pci_read_byte(dev, 0x88) != new) { - msg_pinfo("Setting register to set 0x%x to 0x%x on %s " + msg_pinfo("Setting register to 0x%x to 0x%x on %s " "failed (WARNING ONLY).\n", 0x88, new, name); } } @@ -1196,7 +1196,7 @@ const struct penable chipset_enables[] = { {0x8086, 0x1c46, NT, "Intel", "P67", enable_flash_pch6}, {0x8086, 0x1c47, NT, "Intel", "UM67", enable_flash_pch6}, {0x8086, 0x1c49, NT, "Intel", "HM65", enable_flash_pch6}, - {0x8086, 0x1c4a, NT, "Intel", "H67", enable_flash_pch6}, + {0x8086, 0x1c4a, OK, "Intel", "H67", enable_flash_pch6}, {0x8086, 0x1c4b, NT, "Intel", "HM67", enable_flash_pch6}, {0x8086, 0x1c4c, NT, "Intel", "Q65", enable_flash_pch6}, {0x8086, 0x1c4d, NT, "Intel", "QS67", enable_flash_pch6}, @@ -1207,6 +1207,8 @@ const struct penable chipset_enables[] = { {0x8086, 0x1c54, NT, "Intel", "C204", enable_flash_pch6}, {0x8086, 0x1c56, NT, "Intel", "C206", enable_flash_pch6}, {0x8086, 0x1c5c, NT, "Intel", "H61", enable_flash_pch6}, + {0x8086, 0x1d40, OK, "Intel", "X79", enable_flash_ich10}, /* FIXME: when datasheet is available */ + {0x8086, 0x1d41, NT, "Intel", "X79", enable_flash_ich10}, /* FIXME: when datasheet is available */ {0x8086, 0x2410, OK, "Intel", "ICH", enable_flash_ich_4e}, {0x8086, 0x2420, OK, "Intel", "ICH0", enable_flash_ich_4e}, {0x8086, 0x2440, OK, "Intel", "ICH2", enable_flash_ich_4e}, @@ -1249,7 +1251,7 @@ const struct penable chipset_enables[] = { {0x8086, 0x3b01, NT, "Intel", "3400 Mobile", enable_flash_pch5}, {0x8086, 0x3b02, NT, "Intel", "P55", enable_flash_pch5}, {0x8086, 0x3b03, NT, "Intel", "PM55", enable_flash_pch5}, - {0x8086, 0x3b06, NT, "Intel", "H55", enable_flash_pch5}, + {0x8086, 0x3b06, OK, "Intel", "H55", enable_flash_pch5}, {0x8086, 0x3b07, OK, "Intel", "QM57", enable_flash_pch5}, {0x8086, 0x3b08, NT, "Intel", "H57", enable_flash_pch5}, {0x8086, 0x3b09, NT, "Intel", "HM55", enable_flash_pch5}, diff --git a/dmi.c b/dmi.c index 8f78376..5f64b94 100644 --- a/dmi.c +++ b/dmi.c @@ -81,6 +81,7 @@ static const struct { {0x0e, 1, "Sub Notebook"}, {0x11, 0, "Main Server Chassis"}, {0x17, 0, "Rack Mount Chassis"}, + {0x18, 0, "Sealed-case PC"}, /* used by Supermicro (X8SIE) */ }; #define DMI_COMMAND_LEN_MAX 260 diff --git a/flashchips.c b/flashchips.c index 7e7f47d..5ee8210 100644 --- a/flashchips.c +++ b/flashchips.c @@ -1544,7 +1544,7 @@ const struct flashchip flashchips[] = { .total_size = 4096, .page_size = 256, .feature_bits = FEATURE_WRSR_WREN, - .tested = TEST_UNTESTED, + .tested = TEST_OK_PROBE, .probe = probe_spi_rdid, .probe_timing = TIMING_ZERO, .block_erasers = @@ -3768,13 +3768,13 @@ const struct flashchip flashchips[] = { .model_id = INTEL_28F001T, .total_size = 128, .page_size = 128 * 1024, /* 112k + 2x4k + 8k */ - .tested = TEST_UNTESTED, + .tested = TEST_OK_PR, .probe = probe_jedec, .probe_timing = TIMING_ZERO, /* Datasheet has no timing info specified */ .block_erasers = { { - .eraseblocks = { + .eraseblocks = { {112 * 1024, 1}, {4 * 1024, 2}, {8 * 1024, 1}, @@ -4488,7 +4488,7 @@ const struct flashchip flashchips[] = { { .vendor = "Macronix", - .name = "MX29F002B", + .name = "MX29F002(N)B", .bustype = BUS_PARALLEL, .manufacture_id = MACRONIX_ID, .model_id = MACRONIX_MX29F002B, @@ -4520,7 +4520,7 @@ const struct flashchip flashchips[] = { { .vendor = "Macronix", - .name = "MX29F002T", + .name = "MX29F002(N)T", .bustype = BUS_PARALLEL, .manufacture_id = MACRONIX_ID, .model_id = MACRONIX_MX29F002T, @@ -5637,7 +5637,7 @@ const struct flashchip flashchips[] = { { .vendor = "SST", - .name = "SST25VF010.REMS", + .name = "SST25VF010", .bustype = BUS_SPI, .manufacture_id = SST_ID, .model_id = SST_SST25VF010_REMS, @@ -5775,7 +5775,7 @@ const struct flashchip flashchips[] = { { .vendor = "SST", - .name = "SST25VF040.REMS", + .name = "SST25VF040", .bustype = BUS_SPI, .manufacture_id = SST_ID, .model_id = SST_SST25VF040_REMS, @@ -6125,7 +6125,7 @@ const struct flashchip flashchips[] = { .total_size = 512, .page_size = 4096, .feature_bits = FEATURE_EITHER_RESET, - .tested = TEST_OK_PRE, + .tested = TEST_OK_PREW, .probe = probe_jedec, .probe_timing = 1, /* 150 ns */ .block_erasers = @@ -6610,7 +6610,7 @@ const struct flashchip flashchips[] = { .total_size = 512, .page_size = 64 * 1024, .feature_bits = FEATURE_EITHER_RESET | FEATURE_REGISTERMAP, - .tested = TEST_OK_PRE, + .tested = TEST_OK_PREW, .probe = probe_jedec, .probe_timing = 1, /* 150ns */ .block_erasers = @@ -6729,7 +6729,7 @@ const struct flashchip flashchips[] = { */ { .vendor = "ST", - .name = "M25P05.RES", + .name = "M25P05", .bustype = BUS_SPI, .manufacture_id = 0, /* Not used. */ .model_id = ST_M25P05_RES, @@ -6784,7 +6784,7 @@ const struct flashchip flashchips[] = { /* The ST M25P10 has the same problem as the M25P05. */ { .vendor = "ST", - .name = "M25P10.RES", + .name = "M25P10", .bustype = BUS_SPI, .manufacture_id = 0, /* Not used. */ .model_id = ST_M25P10_RES, @@ -6837,7 +6837,7 @@ const struct flashchip flashchips[] = { }, { - .vendor = "ST", + .vendor = "ST", /* Numonyx */ .name = "M25P40", .bustype = BUS_SPI, .manufacture_id = ST_ID, diff --git a/flashchips.h b/flashchips.h index ff49d31..e8b46ad 100644 --- a/flashchips.h +++ b/flashchips.h @@ -369,8 +369,8 @@ #define MACRONIX_MX25L3235D 0x5E16 /* MX25L3225D/MX25L3235D/MX25L3237D */ #define MACRONIX_MX29F001B 0x19 #define MACRONIX_MX29F001T 0x18 -#define MACRONIX_MX29F002B 0x34 /* Same as MX29F002NB */ -#define MACRONIX_MX29F002T 0xB0 /* Same as MX29F002NT */ +#define MACRONIX_MX29F002B 0x34 /* Same as MX29F002NB; N has reset pin n/c. */ +#define MACRONIX_MX29F002T 0xB0 /* Same as MX29F002NT; N has reset pin n/c. */ #define MACRONIX_MX29F004B 0x46 #define MACRONIX_MX29F004T 0x45 #define MACRONIX_MX29F022T 0x36 /* Same as MX29F022NT */ @@ -474,7 +474,7 @@ #define SST_SST25VF040_REMS 0x44 /* REMS or RES opcode, same as SST25LF040A */ #define SST_SST25VF040B 0x258D #define SST_SST25VF040B_REMS 0x8D /* REMS or RES opcode */ -#define SST_SST25VF080_REMS 0x80 /* REMS or RES opcode */ +#define SST_SST25VF080_REMS 0x80 /* REMS or RES opcode, same as SST25LF080A */ #define SST_SST25VF080B 0x258E #define SST_SST25VF080B_REMS 0x8E /* REMS or RES opcode */ #define SST_SST25VF016B 0x2541 @@ -526,7 +526,7 @@ * ST25P chips are SPI, first byte of device ID is memory type, second * byte of device ID is related to log(bitsize) at least for some chips. */ -#define ST_ID 0x20 /* ST / SGS/Thomson */ +#define ST_ID 0x20 /* ST / SGS/Thomson / Numonyx (later acquired by Micron) */ #define ST_M25P05A 0x2010 #define ST_M25P05_RES 0x10 /* Same code as M25P10. */ #define ST_M25P10A 0x2011 diff --git a/nicintel.c b/nicintel.c index 5410523..f94cbc9 100644 --- a/nicintel.c +++ b/nicintel.c @@ -28,7 +28,7 @@ uint8_t *nicintel_control_bar; const struct pcidev_status nics_intel[] = { {PCI_VENDOR_ID_INTEL, 0x1209, NT, "Intel", "8255xER/82551IT Fast Ethernet Controller"}, - {PCI_VENDOR_ID_INTEL, 0x1229, NT, "Intel", "82557/8/9/0/1 Ethernet Pro 100"}, + {PCI_VENDOR_ID_INTEL, 0x1229, OK, "Intel", "82557/8/9/0/1 Ethernet Pro 100"}, {}, }; diff --git a/print.c b/print.c index f0bd477..66eb144 100644 --- a/print.c +++ b/print.c @@ -431,9 +431,11 @@ const struct board_info boards_known[] = { B("ASUS", "A8V Deluxe", 1, "http://www.asus.com/product.aspx?P_ID=tvpdgPNCPaABZRVU";, NULL), B("ASUS", "A8V-E Deluxe", 1, "http://www.asus.com/product.aspx?P_ID=hQBPIJWEZnnGAZEh";, NULL), B("ASUS", "A8V-E SE", 1, "http://www.asus.com/product.aspx?P_ID=VMfiJJRYTHM4gXIi";, "See http://www.coreboot.org/pipermail/coreboot/2007-October/026496.html";), + B("ASUS", "Crosshair IV Extreme", 1, "http://www.asus.com/product.aspx?P_ID=lt1ShF6xEn3rlLe7";, NULL), B("ASUS", "E35M1-I DELUXE", 1, "http://www.asus.com/product.aspx?P_ID=9BmKhMwWCwqyl1lz";, NULL), B("ASUS", "K8V", 1, "http://www.asus.com/product.aspx?P_ID=fG2KZOWF7v6MRFRm";, NULL), B("ASUS", "K8V SE Deluxe", 1, "http://www.asus.com/product.aspx?P_ID=65HeDI8XM1u6Uy6o";, NULL), + B("ASUS", "K8V-X", 1, NULL, NULL), B("ASUS", "K8V-X SE", 1, "http://www.asus.com/product.aspx?P_ID=lzDXlbBVHkdckHVr";, NULL), B("ASUS", "M2A-MX", 1, "http://www.asus.com/product.aspx?P_ID=BmaOnPewi1JgltOZ";, NULL), B("ASUS", "M2A-VM", 1, "http://www.asus.com/product.aspx?P_ID=St3pWpym8xXpROQS";, "See http://www.coreboot.org/pipermail/coreboot/2007-September/025281.html";), @@ -469,6 +471,7 @@ const struct board_info boards_known[] = { B("ASUS", "P4C800-E Deluxe", 1, "http://www.asus.com/product.aspx?P_ID=cFuVCr9bXXCckmcK";, NULL), B("ASUS", "P4P800", 1, "http://www.asus.com/product.aspx?P_ID=DYt1Et9MlBChqzLb";, NULL), B("ASUS", "P4P800-E Deluxe", 1, "http://www.asus.com/product.aspx?P_ID=INIJUvLlif7LHp3g";, NULL), + B("ASUS", "P4P800-VM", 1, NULL, NULL), B("ASUS", "P4SC-E", 1, "ftp://ftp.asus.com.tw/pub/ASUS/mb/sock478/p4sc-e/";, "Part of ASUS Terminator P4 533 barebone system"), B("ASUS", "P4SD-LA", 1, "http://h10025.www1.hp.com/ewfrf/wc/document?docname=c00022505";, NULL), B("ASUS", "P4S533-X", 1, "ftp://ftp.asus.com.tw/pub/ASUS/mb/sock478/p4s533-x/";, NULL), @@ -496,6 +499,7 @@ const struct board_info boards_known[] = { B("ASUS", "P6T Deluxe", 1, "http://www.asus.com/product.aspx?P_ID=vXixf82co6Q5v0BZ";, NULL), B("ASUS", "P6T Deluxe V2", 1, "http://www.asus.com/product.aspx?P_ID=iRlP8RG9han6saZx";, NULL), B("ASUS", "P7H57D-V EVO", 1, "http://www.asus.com/Motherboards/Intel_Socket_1156/P7H57DV_EVO/";, NULL), + B("ASUS", "P7H55-M LX", 0, NULL, "flashrom works correctly, but GbE LAN is nonworking (probably due to a missing/bogus MAC address; see http://www.flashrom.org/pipermail/flashrom/2011-July/007432.html and http://ubuntuforums.org/showthread.php?t=1534389 for a possible workaround)"), B("ASUS", "Z8NA-D6C", 1, "http://www.asus.com/product.aspx?P_ID=k81cpN8uEB01BpQ6";, NULL), B("BCOM", "WinNET100", 1, "http://www.coreboot.org/BCOM_WINNET100";, "Used in the IGEL-316 thin client."), B("Biostar", "M6TBA", 0, "ftp://ftp.biostar-usa.com/manuals/M6TBA/";, "No public report found. Owned by Uwe Hermann <[email protected]>. May work now."), @@ -512,6 +516,7 @@ const struct board_info boards_known[] = { B("Elitegroup", "K7S5A", 1, "http://www.ecs.com.tw/ECSWebSite/Products/ProductsDetail.aspx?detailid=279&CategoryID=1&DetailName=Specification&MenuID=1&LanID=0";, NULL), B("Elitegroup", "K7S6A", 1, "http://www.ecs.com.tw/ECSWebSite/Products/ProductsDetail.aspx?detailid=77&CategoryID=1&DetailName=Specification&MenuID=52&LanID=0";, NULL), B("Elitegroup", "K7VTA3", 1, "http://www.ecs.com.tw/ECSWebSite/Products/ProductsDetail.aspx?detailid=264&CategoryID=1&DetailName=Specification&MenuID=52&LanID=0";, NULL), + B("Elitegroup", "P4M800PRO-M (V1.0A)", 1, "http://www.ecs.com.tw/ECSWebSite_2007/Products/ProductsDetail.aspx?CategoryID=1&DetailID=574&DetailName=Feature&MenuID=52&LanID=0";, NULL), B("Elitegroup", "P6IWP-Fe", 1, "http://www.ecs.com.tw/ECSWebSite_2007/Products/ProductsDetail.aspx?CategoryID=1&TypeID=3&DetailID=95&DetailName=Feature&MenuID=1&LanID=0";, NULL), B("Elitegroup", "P6VAP-A+", 1, "http://www.ecs.com.tw/ECSWebSite/Products/ProductsDetail.aspx?detailid=117&CategoryID=1&DetailName=Specification&MenuID=1&LanID=0";, NULL), B("Elitegroup", "RS485M-M", 1, "http://www.ecs.com.tw/ECSWebSite_2007/Products/ProductsDetail.aspx?CategoryID=1&DetailID=654&DetailName=Feature&MenuID=1&LanID=0";, NULL), @@ -567,6 +572,7 @@ const struct board_info boards_known[] = { B("GIGABYTE", "GA-MA790GP-DS4H", 1, "http://www.gigabyte.com/products/product-page.aspx?pid=2887";, NULL), B("GIGABYTE", "GA-MA790XT-UD4P (rev. 1.0)", 1, "http://www.gigabyte.com/products/product-page.aspx?pid=3010";, NULL), B("GIGABYTE", "GA-P55A-UD4 (rev. 1.0)", 1, "http://www.gigabyte.com/products/product-page.aspx?pid=3436";, NULL), + B("GIGABYTE", "GA-X58A-UD7 (rev. 2.0)", 1, NULL, NULL), B("HP", "e-Vectra P2706T", 1, "http://h20000.www2.hp.com/bizsupport/TechSupport/Home.jsp?lang=en&cc=us&prodSeriesId=77515&prodTypeId=12454";, NULL), B("HP", "ProLiant DL145 G3", 1, "http://h20000.www2.hp.com/bizsupport/TechSupport/Document.jsp?objectID=c00816835&lang=en&cc=us&taskId=101&prodSeriesId=3219755&prodTypeId=15351";, NULL), B("HP", "ProLiant DL165 G6", 1, "http://h10010.www1.hp.com/wwpc/us/en/sm/WF05a/15351-15351-3328412-241644-3328421-3955644.html";, NULL), @@ -579,6 +585,7 @@ const struct board_info boards_known[] = { B("IBM", "x3455", 1, "http://www-03.ibm.com/systems/x/hardware/rack/x3455/index.html";, NULL), B("IEI", "PICOe-9452", 1, "http://www.ieiworld.com/product_groups/industrial/content.aspx?keyword=WSB&gid=00001000010000000001&cid=08125380291060861658&id=08142308605814597144";, NULL), B("Intel", "D201GLY", 1, "http://www.intel.com/support/motherboards/desktop/d201gly/index.htm";, NULL), + B("Intel", "D865GLC", 0, NULL, "ICH5 with BIOS lock enable, see http://paste.flashrom.org/view.php?id=775";), B("Intel", "DG45ID", 0, "http://www.intel.com/products/desktop/motherboards/dg45id/dg45id-overview.htm";, "Probing works (Winbond W25x32, 4096 kB, SPI), but parts of the flash are problematic: descriptor is r/o (conforming to ICH reqs), ME is locked."), B("Intel", "EP80759", 1, NULL, NULL), B("Intel", "Foxhollow", 1, NULL, "Intel reference board."), @@ -647,6 +654,7 @@ const struct board_info boards_known[] = { B("Shuttle", "AK38N", 1, "http://eu.shuttle.com/en/desktopdefault.aspx/tabid-36/558_read-9889/";, NULL), B("Shuttle", "AV11V30", 1, NULL, NULL), B("Shuttle", "FD37", 1, "http://www.shuttle.eu/products/discontinued/barebones/sd37p2/";, NULL), + B("Shuttle", "FH67", 1, "http://www.shuttle.eu/products/mini-pc/sh67h3/specification/";, NULL), B("Shuttle", "FN25", 1, "http://www.shuttle.eu/products/discontinued/barebones/sn25p/?0=";, NULL), B("Shuttle", "X50/X50(B)", 1, "http://au.shuttle.com/product_detail_spec.jsp?PI=1241";, NULL), B("Soyo", "SY-5VD", 0, "http://www.soyo.com/content/Downloads/163/&c=80&p=464&l=English";, "No public report found. Owned by Uwe Hermann <[email protected]>. May work now."), @@ -664,6 +672,7 @@ const struct board_info boards_known[] = { B("Supermicro", "X8DT3", 1, "http://www.supermicro.com/products/motherboard/QPI/5500/X8DT3.cfm";, NULL), B("Supermicro", "X8DTH-6F", 1, "http://www.supermicro.com/products/motherboard/QPI/5500/X8DTH-6F.cfm";, NULL), B("Supermicro", "X8DTT-F", 1, "http://www.supermicro.com/products/motherboard/QPI/5500/X8DTT-F.cfm";, NULL), + B("Supermicro", "X8DTU-6TF+", 0, "http://www.supermicro.com/products/motherboard/QPI/5500/X8DTU_.cfm?TYP=SAS&LAN=10";, "Probing works (Atmel AT25DF321A, 4096 kB, SPI), but parts of the flash are problematic: descriptor is r/o (conforming to ICH reqs), ME region is locked."), B("Supermicro", "X8DTU-F", 1, "http://www.supermicro.com/products/motherboard/QPI/5500/X8DTU-F.cfm";, NULL), B("Supermicro", "X8SIE(-F)", 0, "http://www.supermicro.com/products/motherboard/Xeon3000/3400/X8SIE.cfm?IPMI=N&TYP=LN2";, "Requires unlocking the ME although the registers are set up correctly by the descriptor/BIOS already (tested with swseq and hwseq)."), B("Supermicro", "X8STi", 1, "http://www.supermicro.com/products/motherboard/Xeon3000/X58/X8STi.cfm";, NULL), @@ -683,6 +692,7 @@ const struct board_info boards_known[] = { B("Tyan", "S2891 (Thunder K8SRE)", 1, "http://www.tyan.com/product_board_detail.aspx?pid=144";, NULL), B("Tyan", "S2892 (Thunder K8SE)", 1, "http://www.tyan.com/product_board_detail.aspx?pid=145";, NULL), B("Tyan", "S2895 (Thunder K8WE)", 1, "http://www.tyan.com/archive/products/html/thunderk8we.html";, NULL), + B("Tyan", "S2912 (Thunder n3600R)", 1, "http://www.tyan.com/product_board_detail.aspx?pid=157";, NULL), B("Tyan", "S2915 (Thunder n6650W)", 1, "http://tyan.com/product_board_detail.aspx?pid=163";, NULL), B("Tyan", "S2915-E (Thunder n6650W)", 1, "http://tyan.com/product_SKU_spec.aspx?ProductType=MB&pid=541&SKU=600000041";, NULL), B("Tyan", "S2933 (Thunder n3600S)", 1, "http://tyan.com/product_SKU_spec.aspx?ProductType=MB&pid=478&SKU=600000063";, NULL), @@ -712,6 +722,7 @@ const struct board_info boards_known[] = { B("VIA", "pc2500e", 1, "http://www.via.com.tw/en/initiatives/empowered/pc2500_mainboard/index.jsp";, NULL), B("VIA", "PC3500G", 1, "http://www.via.com.tw/en/initiatives/empowered/pc3500_mainboard/index.jsp";, NULL), B("VIA", "VB700X", 1, "http://www.via.com.tw/en/products/mainboards/motherboards.jsp?motherboard_id=490";, NULL), + B("ZOTAC", "GeForce 8200", 1, "http://pden.zotac.com/index.php?page=shop.product_details&product_id=129&category_id=92";, NULL), B("ZOTAC", "ZBOX HD-ID11", 1, "http://pdde.zotac.com/index.php?page=shop.product_details&product_id=240&category_id=75";, NULL), #endif diff --git a/programmer.h b/programmer.h index 6a28dbe..70f3c09 100644 --- a/programmer.h +++ b/programmer.h @@ -424,9 +424,6 @@ extern const struct pcidev_status nics_intel[]; /* nicintel_spi.c */ #if CONFIG_NICINTEL_SPI == 1 int nicintel_spi_init(void); -int nicintel_spi_send_command(unsigned int writecnt, unsigned int readcnt, - const unsigned char *writearr, unsigned char *readarr); -void nicintel_spi_chip_writeb(uint8_t val, chipaddr addr); extern const struct pcidev_status nics_intel_spi[]; #endif -- 1.7.1 _______________________________________________ flashrom mailing list [email protected] http://www.flashrom.org/mailman/listinfo/flashrom
