If the function fails it returns 0. All callers have been made aware of this and are prepared to handle it.
Signed-off-by: Niklas Söderlund <[email protected]> --- atahpt.c | 2 ++ drkaiser.c | 2 ++ gfxnvidia.c | 2 ++ nic3com.c | 2 ++ nicintel.c | 7 +++---- nicintel_spi.c | 2 ++ nicnatsemi.c | 2 ++ nicrealtek.c | 2 ++ ogp_spi.c | 2 ++ pcidev.c | 6 +++--- satamv.c | 5 ++--- satasii.c | 3 ++- 12 files changed, 26 insertions(+), 11 deletions(-) diff --git a/atahpt.c b/atahpt.c index b692b88..4c1b13e 100644 --- a/atahpt.c +++ b/atahpt.c @@ -71,6 +71,8 @@ int atahpt_init(void) return 1; io_base_addr = pcidev_init(PCI_BASE_ADDRESS_4, ata_hpt); + if (!io_base_addr) + return 1; /* Enable flash access. */ reg32 = pci_read_long(pcidev_dev, REG_FLASH_ACCESS); diff --git a/drkaiser.c b/drkaiser.c index d4b6120..ffabf9b 100644 --- a/drkaiser.c +++ b/drkaiser.c @@ -71,6 +71,8 @@ int drkaiser_init(void) return 1; addr = pcidev_init(PCI_BASE_ADDRESS_2, drkaiser_pcidev); + if (!addr) + return 1; /* Write magic register to enable flash write. */ rpci_write_word(pcidev_dev, PCI_MAGIC_DRKAISER_ADDR, diff --git a/gfxnvidia.c b/gfxnvidia.c index 457172d..fe2362a 100644 --- a/gfxnvidia.c +++ b/gfxnvidia.c @@ -95,6 +95,8 @@ int gfxnvidia_init(void) return 1; io_base_addr = pcidev_init(PCI_BASE_ADDRESS_0, gfx_nvidia); + if (!io_base_addr) + return 1; io_base_addr += 0x300000; msg_pinfo("Detected NVIDIA I/O base address: 0x%x.\n", io_base_addr); diff --git a/nic3com.c b/nic3com.c index 4df720f..27d9506 100644 --- a/nic3com.c +++ b/nic3com.c @@ -91,6 +91,8 @@ int nic3com_init(void) return 1; io_base_addr = pcidev_init(PCI_BASE_ADDRESS_0, nics_3com); + if (!io_base_addr) + return 1; id = pcidev_dev->device_id; diff --git a/nicintel.c b/nicintel.c index f2d4529..7d6fa94 100644 --- a/nicintel.c +++ b/nicintel.c @@ -77,11 +77,10 @@ int nicintel_init(void) if (get_io_perms()) return 1; - /* No need to check for errors, pcidev_init() will not return in case - * of errors. - * FIXME: BAR2 is not available if the device uses the CardBus function. - */ + /* FIXME: BAR2 is not available if the device uses the CardBus function. */ addr = pcidev_init(PCI_BASE_ADDRESS_2, nics_intel); + if (!addr) + return 1; nicintel_bar = physmap("Intel NIC flash", addr, NICINTEL_MEMMAP_SIZE); if (nicintel_bar == ERROR_PTR) diff --git a/nicintel_spi.c b/nicintel_spi.c index 7eb3af3..af7347b 100644 --- a/nicintel_spi.c +++ b/nicintel_spi.c @@ -171,6 +171,8 @@ int nicintel_spi_init(void) return 1; io_base_addr = pcidev_init(PCI_BASE_ADDRESS_0, nics_intel_spi); + if (!io_base_addr) + return 1; nicintel_spibar = physmap("Intel Gigabit NIC w/ SPI flash", io_base_addr, 4096); diff --git a/nicnatsemi.c b/nicnatsemi.c index c39637a..d16984d 100644 --- a/nicnatsemi.c +++ b/nicnatsemi.c @@ -63,6 +63,8 @@ int nicnatsemi_init(void) return 1; io_base_addr = pcidev_init(PCI_BASE_ADDRESS_0, nics_natsemi); + if (!io_base_addr) + return 1; if (register_shutdown(nicnatsemi_shutdown, NULL)) return 1; diff --git a/nicrealtek.c b/nicrealtek.c index f808e06..17a3172 100644 --- a/nicrealtek.c +++ b/nicrealtek.c @@ -65,6 +65,8 @@ int nicrealtek_init(void) return 1; io_base_addr = pcidev_init(PCI_BASE_ADDRESS_0, nics_realtek); + if (!io_base_addr) + return 1; if (register_shutdown(nicrealtek_shutdown, NULL)) return 1; diff --git a/ogp_spi.c b/ogp_spi.c index 8502847..dc62d7d 100644 --- a/ogp_spi.c +++ b/ogp_spi.c @@ -132,6 +132,8 @@ int ogp_spi_init(void) return 1; io_base_addr = pcidev_init(PCI_BASE_ADDRESS_0, ogp_spi); + if (!io_base_addr) + return 1; ogp_spibar = physmap("OGP registers", io_base_addr, 4096); diff --git a/pcidev.c b/pcidev.c index e8b4dc1..c32027c 100644 --- a/pcidev.c +++ b/pcidev.c @@ -207,7 +207,7 @@ uintptr_t pcidev_init(int bar, const struct pcidev_status *devs) if (pcidev_bdf != NULL) { if ((msg = pci_filter_parse_slot(&filter, pcidev_bdf))) { msg_perr("Error: %s\n", msg); - exit(1); + return 0; } } free(pcidev_bdf); @@ -228,13 +228,13 @@ uintptr_t pcidev_init(int bar, const struct pcidev_status *devs) /* Only continue if exactly one supported PCI dev has been found. */ if (found == 0) { msg_perr("Error: No supported PCI device found.\n"); - exit(1); + return 0; } else if (found > 1) { msg_perr("Error: Multiple supported PCI devices found. " "Use 'flashrom -p xxxx:pci=bb:dd.f' \n" "to explicitly select the card with the given BDF " "(PCI bus, device, function).\n"); - exit(1); + return 0; } return curaddr; diff --git a/satamv.c b/satamv.c index 0b83a14..f23af3b 100644 --- a/satamv.c +++ b/satamv.c @@ -89,10 +89,9 @@ int satamv_init(void) return 1; /* BAR0 has all internal registers memory mapped. */ - /* No need to check for errors, pcidev_init() will not return in case - * of errors. - */ addr = pcidev_init(PCI_BASE_ADDRESS_0, satas_mv); + if (!addr) + return 1; mv_bar = physmap("Marvell 88SX7042 registers", addr, 0x20000); if (mv_bar == ERROR_PTR) diff --git a/satasii.c b/satasii.c index 75378be..ac70129 100644 --- a/satasii.c +++ b/satasii.c @@ -73,7 +73,8 @@ int satasii_init(void) if (get_io_perms()) return 1; - pcidev_init(PCI_BASE_ADDRESS_0, satas_sii); + if (!pcidev_init(PCI_BASE_ADDRESS_0, satas_sii)) + return 1; id = pcidev_dev->device_id; -- 1.7.11.1 _______________________________________________ flashrom mailing list [email protected] http://www.flashrom.org/mailman/listinfo/flashrom
