On Fri, 6 Jul 2012 07:14:15 +0200 Stefan Tauner <[email protected]> wrote:
> On Sat, 9 Jun 2012 14:51:15 +0200 > [email protected] wrote: > > > Numonyx/Micron N25Q128 is used on new X9 motherboards from Supermicro > > (X9DRT, ...) > > > > Specs are availbale on Micron WWW site: > > http://www.micron.com/~/media/Documents/Products/Data%20Sheet/NOR%20Flash/Serial%20NOR/N25Q/N25Q_128_3_Volt_with_boot_sector.pdf > > > > Following patch add this chip to flashrom. Probe is OK. > > Due to Manageability Engine, some work is required before being able to > > test READ/ERASE/WRITE... > > […] > hello and thanks for your patch! > this chip is a bit complicated and we cant merge the patch as it is. > they have used the same plane RDID for multiple variants of the chip. > some attributes are not important for flashrom and can be ignored, but > some are very important, namely the boot sector layout. quote from p.52: > > > The N25Q128 is available in the following architecture versions: > > Bottom version, 64 KB uniform sectors plus 8 bottom boot sectors (each with > > 16 > > subsectors), > > Top version, 64 KB uniform sectors plus 8 top boot sectors (each with 16 > > subsectors) > > Uniform version, 64 KB uniform sectors without any boot sectors and > > subsectors. > > the good news is that this differences can be detected by an extended > RDID command in its 5th byte (1 manufacturer, 2 device, 1 length of the > following extended data, the first EDID byte we want), see table 15. > of this 5th byte we need to look at the first two bits to determine the > architecture, see table 16. > > our current infrastructure (probe_spi_rdid_generic) cant handle that, > but should... so we will plan a change, but please dont expect it to > happen too soon. A patch exists now that adds this functionality, but it is not merged yet. > the bad news is that i am not even sure if the subsector erase commands > work as flashrom expects. flashrom wants to use the same erase opcode > for the hole address space, even for non-uniform layouts. this usually > works fine, but afaics it is not specified in the datasheet what > happens if one uses the subsector erase opcode on a non-subsector *on > devices that actually have subsectors* (the emphasis stems from the > fact that it *is* defined, that the subsector erase command is ignore > by the uniform model: "Any Subsector Erase (SSE) instruction in devices > with uniform architecture (meaning no boot sectors with subsectors) is > rejected without having any effects on the device." (p. 98). I missed a bit in the old datasheet (rev. 7 from may 2011) previously: "subsector erase (SSE) instruction (only available on the 8 boot sectors at the bottom or top addressable area of a device with a dedicated part number)" (p. 24). We still don't know what would happen exactly, but certainly not what we would like to. And there is a new datasheet (rev. L from June 12 [1]) that does specify uniform layouts only, but all of them actually *do* include 4 kB subsectors. Also there is a uniform version with 1.8V VCC now[2]. So we have different options, besides asking micron how we could differentiate them or get innovative and check available opcodes…: - disable the 4 kB erasers on all chips to avoid any scary messages (down side: 64 kB minimum erase resolution instead of 4 kB; advantage: we could merge all three 3V versions into one). - enable (some of) them and hope no user gets a stroke :) My current updated (but unpublished) patch disables the 4kB erasers completely, but keeps all 3 distinct 3V versions as separate entries. > […] > regarding the ME: […] Do you have any news regarding this Frederic? [1]: http://www.micron.com/~/media/Documents/Products/Data%20Sheet/NOR%20Flash/Serial%20NOR/N25Q/n25q_128mb_3v_65nm.pdf [2]: http://www.micron.com/~/media/Documents/Products/Data%20Sheet/NOR%20Flash/Serial%20NOR/N25Q/n25q_128mb_1_8v_65nm.pdf -- Kind regards/Mit freundlichen Grüßen, Stefan Tauner _______________________________________________ flashrom mailing list [email protected] http://www.flashrom.org/mailman/listinfo/flashrom
