This fixes 5 errors found running codespell on the sources. Codespell is at https://github.com/lucasdemarchi/codespell
Signed-off-by: Daniele Forsi <[email protected]> Index: Documentation/serprog-protocol.txt =================================================================== --- Documentation/serprog-protocol.txt (revision 1830) +++ Documentation/serprog-protocol.txt (working copy) @@ -74,7 +74,7 @@ Send and receive bytes via SPI. Maximum slen is Q_WRNMAXLEN in case Q_BUSTYPE returns SPI only or S_BUSTYPE was used to set SPI exclusively before. Same for rlen and Q_RDNMAXLEN. - This operation is immediate, meaning it doesnt use the operation buffer. + This operation is immediate, meaning it doesn't use the operation buffer. 0x14 (S_SPI_FREQ): Set the SPI clock frequency. The 32-bit value indicates the requested frequency in Hertz. Value 0 is reserved and should Index: atavia.c =================================================================== --- atavia.c (revision 1830) +++ atavia.c (working copy) @@ -113,7 +113,7 @@ } msg_pdbg2("\n%s: %s after %d tries (access=0x%02x, status=0x%02x)\n", - __func__, ready ? "suceeded" : "failed", try, access, status); + __func__, ready ? "succeeded" : "failed", try, access, status); atavia_prettyprint_access(access); return ready; } Index: dmi.c =================================================================== --- dmi.c (revision 1830) +++ dmi.c (working copy) @@ -188,7 +188,7 @@ /* - If a short entry is found (less than 4 bytes), not only it * is invalid, but we cannot reliably locate the next entry. * - If the length value indicates that this structure spreads - * accross the table border, something is fishy too. + * across the table border, something is fishy too. * Better stop at this point, and let the user know his/her * table is broken. */ Index: flashchips.c =================================================================== --- flashchips.c (revision 1830) +++ flashchips.c (working copy) @@ -6327,7 +6327,7 @@ .block_erase = spi_block_erase_c7, }, }, - .printlock = spi_prettyprint_status_register_bp3_srwd, /* bit6: Continously Program (CP) mode */ + .printlock = spi_prettyprint_status_register_bp3_srwd, /* bit6: Continuously Program (CP) mode */ .unlock = spi_disable_blockprotect, .write = spi_chip_write_256, .read = spi_chip_read, /* Fast read (0x0B), dual I/O supported */ Index: flashrom.8.tmpl =================================================================== --- flashrom.8.tmpl (revision 1830) +++ flashrom.8.tmpl (working copy) @@ -772,7 +772,7 @@ .B value can be .BR 1 " or " 2 -to select target chip 1 or 2 repectively. The default is target chip 1. +to select target chip 1 or 2 respectively. The default is target chip 1. .SS .BR "rayer_spi " programmer The default I/O base address used for the parallel port is 0x378 and you can use _______________________________________________ flashrom mailing list [email protected] http://www.flashrom.org/mailman/listinfo/flashrom
