Hello, I am testing flashrom on a Rangeley system using coreboot. The flash chip is W25Q64.V. I am using Stefan's refactored support for Baytrail/Rangeley: https://github.com/stefanct/flashrom/tree/intel.
The read operation failed (log attached). Any suggestions to debug it would be appreciated! Thanks, Wen PS: Stefan - I finally got subscribed to the mailing list I think. My system was treating flashrom.org as spam initially. Thanks for responding my earlier email. -----Original Message----- From: "Stefan Tauner" <[email protected]> Sent: Monday, August 11, 2014 6:22pm To: "Wen Wang" <[email protected]> Subject: Re: flashrom Rangeley/Baytrail On Mon, 11 Aug 2014 12:20:15 -0400 "Wen Wang" <[email protected]> wrote: > Hello Stefan, > > I am trying to test the flashrom patch for Rangeley and Baytrail. I read in > your recent blog that you made some updates on top of Martin's patch. I am > very interested in trying your changes. Is it enough if I pull your branch > https://github.com/stefanct/flashrom/tree/intel? I have a Bayley Bay CRB and > a mohonpeak equivalent system to try. Hello, using that branch is fine, yes. Good luck, hopefully you won't need it :) > PS: I was trying to get onto the flashrom mailing list, but for some reason > I never got through. So I have to send an email to you directly. Maybe your server was not accepting mails from the flashrom host and you never got subscribed therefore (the flashrom.org domain had problems in the last weeks for some people which led to some servers not accepting mails from the list). Anyway, you can always send mails to the mailing list without being subscribed, we just have to moderate them manually. Please do so with any logs you create, and optionally you may wanna retry to subscribe... -- Kind regards/Mit freundlichen Grüßen, Stefan Tauner
flashrom v0.9.7-r1832 on Linux 3.3.4-5.fc17.x86_64 (x86_64) flashrom was built with libpci 3.1.9, GCC 4.7.0 20120507 (Red Hat 4.7.0-5), little endian Command line (9 args): ./flashrom -p internal -r backup.bin -c W25Q64.V -o debug.log -V Calibrating delay loop... OS timer resolution is 1 usecs, 582M loops per second, 10 myus = 10 us, 100 myus = 100 us, 1000 myus = 1006 us, 10000 myus = 10021 us, 4 myus = 4 us, OK. Initializing internal programmer Found candidate at: 00000500-00000510 Found coreboot table at 0x00000500. Found candidate at: 00000000-00000270 Found coreboot table at 0x00000000. coreboot table found at 0x7fde5000. coreboot header(24) checksum: 9795 table(624) checksum: d43e entries: 14 Vendor ID: Intel, part ID: Mohon Peak Using Internal DMI decoder. DMI string chassis-type: "Desktop" DMI string system-manufacturer: "Intel" DMI string system-product-name: "Mohon Peak" DMI string system-version: "1.0" DMI string baseboard-manufacturer: "" DMI string baseboard-product-name: "" DMI string baseboard-version: "" Found chipset "Intel Avoton/Rangeley" with PCI ID 8086:1f38. This chipset is marked as untested. If you are using an up-to-date version of flashrom *and* were (not) able to successfully update your firmware with it, then please email a report to [email protected] including a verbose (-V) log. Thank you! Enabling flash write... Root Complex Register Block address = 0xfed1c000 GCS = 0xc01: BIOS Interface Lock-Down: enabled, Boot BIOS Straps: 0x3 (SPI) Top Swap : not enabled 0xfff80000/0xffb80000 FWH IDSEL: 0x0 0xfff00000/0xffb00000 FWH IDSEL: 0x0 0xffe80000/0xffa80000 FWH IDSEL: 0x1 0xffe00000/0xffa00000 FWH IDSEL: 0x1 0xffd80000/0xff980000 FWH IDSEL: 0x2 0xffd00000/0xff900000 FWH IDSEL: 0x2 0xffc80000/0xff880000 FWH IDSEL: 0x3 0xffc00000/0xff800000 FWH IDSEL: 0x3 0xfff80000/0xffb80000 FWH decode enabled 0xfff00000/0xffb00000 FWH decode enabled 0xffe80000/0xffa80000 FWH decode enabled 0xffe00000/0xffa00000 FWH decode enabled 0xffd80000/0xff980000 FWH decode enabled 0xffd00000/0xff900000 FWH decode enabled 0xffc80000/0xff880000 FWH decode enabled 0xffc00000/0xff800000 FWH decode enabled 0xff700000/0xff300000 FWH decode enabled 0xff600000/0xff200000 FWH decode enabled 0xff500000/0xff100000 FWH decode enabled 0xff400000/0xff000000 FWH decode enabled Maximum FWH chip size: 0x100000 bytes SPI_BASE_ADDRESS = 0xfed01000 SPI Read Configuration: prefetching enabled, caching enabled, BIOS_CNTL = 0x09: BIOS Lock Enable: disabled, BIOS Write Enable: enabled 0x04: 0x6000 (HSFS) HSFS: FDONE=0, FCERR=0, AEL=0, BERASE=0, SCIP=0, FDOPSS=1, FDV=1, FLOCKDN=0 Programming OPCODES... program_opcodes: preop=5006 optype=463b opmenu=05d80302c79f0190 done OP Type Pre-OP op[0]: 0x02, write w/ addr, none op[1]: 0x03, read w/ addr, none op[2]: 0xd8, write w/ addr, none op[3]: 0x05, read w/o addr, none op[4]: 0x90, read w/ addr, none op[5]: 0x01, write w/o addr, none op[6]: 0x9f, read w/o addr, none op[7]: 0xc7, write w/o addr, none Pre-OP 0: 0x06, Pre-OP 1: 0x50 0x06: 0x0000 (HSFC) HSFC: FGO=0, FCYCLE=0, FDBC=0, SME=0 0x08: 0x00010000 (FADDR) 0x50: 0x00001a1b (FRAP) BMWAG 0x00, BMRAG 0x00, BRWA 0x1a, BRRA 0x1b 0x54: 0x000f0000 FREG0: Warning: Flash Descriptor region (0x00000000-0x0000ffff) is read-only. 0x58: 0x07ff0200 FREG1: BIOS region (0x00200000-0x007fffff) is read-write. 0x5C: 0x00000fff FREG2: Management Engine region is unused. 0x60: 0x00000fff FREG3: Gigabit Ethernet region is unused. 0x64: 0x00000fff FREG4: Platform Data region is unused. Not all flash regions are freely accessible by flashrom. This is most likely due to an active ME. Please see http://flashrom.org/ME for details. 0x74: 0x00000000 (PR0 is unused) 0x78: 0x00000000 (PR1 is unused) 0x7C: 0x00000000 (PR2 is unused) 0x80: 0x00000000 (PR3 is unused) 0x84: 0x00000000 (PR4 is unused) Writes have been disabled for safety reasons. You can enforce write support with the ich_spi_force programmer option, but you will most likely harm your hardware! If you force flashrom you will get no support if something breaks. On a few mainboards it is possible to enable write access by setting a jumper (see its documentation or the board itself). 0x90: 0x04 (SSFS) SSFS: SCIP=0, FDONE=1, FCERR=0, AEL=0 0x91: 0xf80000 (SSFC) SSFC: SCGO=0, ACS=0, SPOP=0, COP=0, DBC=0, SME=0, SCF=0 0x94: 0x5006 (PREOP) 0x96: 0x463b (OPTYPE) 0x98: 0x05d80302 (OPMENU) 0x9C: 0xc79f0190 (OPMENU+4) 0xC4: 0x00800000 (LVSCC) LVSCC: BES=0x0, WG=0, WSR=0, WEWS=0, EO=0x0, VCL=1 0xC8: 0x00000000 (UVSCC) UVSCC: BES=0x0, WG=0, WSR=0, WEWS=0, EO=0x0, VCL=0 0xD0: 0x00000000 (FPB) Reading flash descriptors mapped by the chipset via FDOC/FDOD... done. === Content Section === FLVALSIG 0x0ff0a55a FLMAP0 0x01040003 FLMAP1 0x09100206 FLMAP2 0x00210020 --- Details --- NR (Number of Regions): 2 FRBA (Flash Region Base Address): 0x040 NC (Number of Components): 1 FCBA (Flash Component Base Address): 0x030 ISL (ICH/PCH Strap Length): 9 FISBA/FPSBA (Flash ICH/PCH Strap Base Address): 0x100 NM (Number of Masters): 3 FMBA (Flash Master Base Address): 0x060 MSL/PSL (MCH/PROC Strap Length): 0 FMSBA (Flash MCH/PROC Strap Base Address): 0x200 === Component Section === FLCOMP 0x00000024 FLILL 0x00000000 --- Details --- Component 1 density: 8 MB Component 2 is not used. Read Clock Frequency: 20 MHz Read ID and Status Clock Freq.: 20 MHz Write and Erase Clock Freq.: 20 MHz Fast Read is not supported. Dual Output Fast Read Support: enabled No forbidden opcodes. === Region Section === FLREG0 0x000f0000 FLREG1 0x07ff0200 FLREG2 0x00000fff FLREG3 0x00000fff FLREG4 0x00000fff --- Details --- Region 0 (Descr.) 0x00000000 - 0x0000ffff Region 1 (BIOS ) 0x00200000 - 0x007fffff Region 2 (ME ) is unused. Region 3 (GbE ) is unused. Region 4 (Platf.) is unused. === Master Section === FLMSTR1 0x1a1b0000 FLMSTR2 0x08090118 FLMSTR3 0xffffffff --- Details --- Descr. BIOS ME GbE Platf. BIOS r rw rw rw ME r rw GbE rw rw rw rw rw OK. No board enable found matching coreboot IDs vendor="Intel", model="Mohon Peak". The following protocols are supported: FWH, SPI. Probing for Winbond W25Q64.V, 8192 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4017 Found Winbond flash chip "W25Q64.V" (8192 kB, SPI) at physical address 0xff800000. Chip status register is 0x00. This chip may contain one-time programmable memory. flashrom cannot read and may never be able to write it, hence it may not be able to completely clone the contents of this chip (see man page for details). Block protection is disabled. Reading flash... Transaction error! SSFS: SCIP=0, FDONE=1, FCERR=1, AEL=0 SSFC: SCGO=0, ACS=0, SPOP=0, COP=1, DBC=63, SME=0, SCF=0 Running OPCODE 0x03 failed at address 0x010000 (payload length was 64). Read operation failed! FAILED. Restoring MMIO space at 0x7f8ca3a3109c Restoring MMIO space at 0x7f8ca3a31098 Restoring MMIO space at 0x7f8ca3a31096 Restoring MMIO space at 0x7f8ca3a31094
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