On Fri, 12 Feb 2016 05:07:26 +0530
Hatim Kanchwala <ha...@hatimak.me> wrote:
> Signed-off-by: Hatim Kanchwala <ha...@hatimak.me>
> ---
> flashchips.c | 41 +++++++++++++++++++++++++++++++++++++++++
> flashchips.h | 3 ++-
> 2 files changed, 43 insertions(+), 1 deletion(-)
>
> diff --git a/flashchips.c b/flashchips.c
> index 26a8d89..12c5c62 100644
> --- a/flashchips.c
> +++ b/flashchips.c
> @@ -6206,26 +6206,67 @@ const struct flashchip flashchips[] = {
> .eraseblocks = { {16 * 1024 * 1024, 1} },
> .block_erase = spi_block_erase_c7,
> }
> },
> .printlock = spi_prettyprint_status_register_bp4_srwd,
> .unlock = spi_disable_blockprotect_bp4_srwd, /* TODO:
> 2nd status reg (read with 0x35) */
> .write = spi_chip_write_256,
> .read = spi_chip_read, /* Fast read (0x0B) and multi
> I/O supported */
> .voltage = {2700, 3600},
> },
>
> {
> .vendor = "GigaDevice",
> + .name = "GD25Q128C",
> + .bustype = BUS_SPI,
> + .manufacture_id = GIGADEVICE_ID,
> + .model_id = GIGADEVICE_GD25Q128,
> + .total_size = 16384,
> + .page_size = 256,
> + /* OTP: 3 * 512B total; read 0x48; write 0x42, erase 0x44 */
I have changed that to 1536B for consistency.
> + /* QPI: enable 0x38, disable 0xFF */
> + .feature_bits = FEATURE_WRSR_WREN | FEATURE_OTP | FEATURE_QPI,
> + .tested = TEST_UNTESTED,
> + .probe = probe_spi_rdid,
> + .probe_timing = TIMING_ZERO,
> + .block_erasers =
> + {
> + {
> + .eraseblocks = { {4 * 1024, 4096} },
> + .block_erase = spi_block_erase_20,
> + }, {
> + .eraseblocks = { {32 * 1024, 512} },
> + .block_erase = spi_block_erase_52,
> + }, {
> + .eraseblocks = { {64 * 1024, 256} },
> + .block_erase = spi_block_erase_d8,
> + }, {
> + .eraseblocks = { {16 * 1024 * 1024, 1} },
> + .block_erase = spi_block_erase_60,
> + }, {
> + .eraseblocks = { {16 * 1024 * 1024, 1} },
> + .block_erase = spi_block_erase_c7,
> + }
> + },
> + /* TODO: 2nd status reg (read 0x35, write 0x31) and 3rd status
> reg (read 0x15, write 0x11) */
That one will be fun... lots of possibilities to lock it down as well.
> + .printlock = spi_prettyprint_status_register_bp4_srwd,
> + .unlock = spi_disable_blockprotect_bp4_srwd,
> + .write = spi_chip_write_256,
> + .read = spi_chip_read, /* Fast read (0x0B) and multi
> I/O supported */
> + .voltage = {2700, 3600},
> + },
> +
> + {
> + .vendor = "GigaDevice",
> .name = "GD25T80",
> .bustype = BUS_SPI,
> .manufacture_id = GIGADEVICE_ID,
> .model_id = GIGADEVICE_GD25T80,
> .total_size = 1024,
> .page_size = 256,
> /* OTP: 256B total; enter 0x3A */
> .feature_bits = FEATURE_WRSR_WREN | FEATURE_OTP,
> .tested = TEST_UNTESTED,
> .probe = probe_spi_rdid,
> .probe_timing = TIMING_ZERO,
> .block_erasers = {
> {
> diff --git a/flashchips.h b/flashchips.h
> index e469363..3ab1e07 100644
> --- a/flashchips.h
> +++ b/flashchips.h
> @@ -361,27 +361,28 @@
> #define FUJITSU_MBM29LV160BE 0x49 /* 16 b mode 0x2249 */
> #define FUJITSU_MBM29LV160TE 0xC4 /* 16 b mode 0x22C4 */
>
> #define GIGADEVICE_ID 0xC8 /* GigaDevice */
> #define GIGADEVICE_GD25T80 0x3114
> #define GIGADEVICE_GD25Q512 0x4010
> #define GIGADEVICE_GD25Q10 0x4011
> #define GIGADEVICE_GD25Q20 0x4012 /* Same as GD25QB */
> #define GIGADEVICE_GD25Q40 0x4013 /* Same as GD25QB */
> #define GIGADEVICE_GD25Q80 0x4014 /* Same as GD25Q80B (which has OTP) */
> #define GIGADEVICE_GD25Q16 0x4015 /* Same as GD25Q16B (which has OTP) */
> #define GIGADEVICE_GD25Q32 0x4016 /* Same as GD25Q32B */
> #define GIGADEVICE_GD25Q64 0x4017 /* Same as GD25Q64B */
> -#define GIGADEVICE_GD25Q128 0x4018 /* GD25Q128B only? */
> +#define GIGADEVICE_GD25Q128 0x4018 /* Same as GD25Q128B and GD25Q128C
> (distinguish by RES/REMS) */
I could not find any reference to a plain GD25Q128, did you?
That's why the old comment was there...
It is not uncommon that manufacturers do not release their first
revision of a chip and thus the first released version is often a B.
Also, they can NOT be distinguished by RES/REMS because they share the
same RES/REMS IDs as well! Also, both support a dual and quad I/O REMS
opcode (0x92 and 0x94).
However, there is even a better way to distinguish them: the C
revision supports SFDP while the B does not according to the DS. Cf.
http://blogs.coreboot.org/blog/2011/06/24/gsoc-2011-flashrom-part-2-sfdp/
> +#define GIGADEVICE_GD25Q128C 0x17
> #define GIGADEVICE_GD25LQ40 0x6013
> #define GIGADEVICE_GD25LQ80 0x6014
> #define GIGADEVICE_GD25LQ16 0x6015
> #define GIGADEVICE_GD25LQ32 0x6016
> #define GIGADEVICE_GD25LQ64 0x6017 /* Same as GD25LQ64B (which is faster)
> */
> #define GIGADEVICE_GD25LQ128 0x6018
> #define GIGADEVICE_GD25VQ41B 0x4213
> #define GIGADEVICE_GD29GL064CAB 0x7E0601
>
> #define HYUNDAI_ID 0xAD /* Hyundai */
> #define HYUNDAI_HY29F400T 0x23 /* Same as HY29F400AT */
> #define HYUNDAI_HY29F800B 0x58 /* Same as HY29F800AB */
> #define HYUNDAI_HY29LV800B 0x5B
Rest looks good, thank you. I'll commit it with the GD25VQ41B patch
later.
--
Kind regards/Mit freundlichen Grüßen, Stefan Tauner
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