It seems to me that, much like conventional processors, FPGAs are designed by people (electrical engineers, I suppose) who don't really understand software, especially dynamic software. I don't have much experience in the hardware field, but I'm working with Christof Teuscher [ http://www.teuscher-lab.com/ext/research ], an EE PhD who's designed, overseen, and reviewed quite a few FPGA based systems over the last decade. He says he's not very interested in FPGAs anymore, largely because of things like memory access bottlenecks and excessively proprietary (that is, sealed and secret) toolchains and interface formats.
Plenty of alternative theories of parallel computation (with varying degrees of rigor) have existed for some time now, from Gul Agha's Actors to Gheorghe Păun's P-systems to Peter Wegner's Interaction Machines to Karl Fant's Invocation Model. I'm excited to see the latest from Neil Gershenfeld's group at MIT (thanks, Jecel!) but it seems that hardly anybody has the money to invest in building genuinely unconventional hardware outside the research labs. The only exception I'm aware of at the moment is GreenArrays [ http://greenarrays.com ], which is Chuck Moore (and friends) self-capitalized startup based on his hardware design work over the last two decades. I visited them during SPLASH (which is why I missed Palsberg's talk) and they seem fairly certain of having real chips for sale in quantity by next summer. They are using the cheapest, oldest fabrication process they can, and they're not interested in publishing papers, but they're actually building actual, practical, genuinely different hardware for sale. I'm still trying to figure if their physical grid of tiny little computers is a good match for Alan Kay's vision of a dynamic network of metaphorical 'little computers', but in any case I think that they deserve a shout-out. Regards, -- Max OrHai On Mon, Nov 1, 2010 at 12:53 PM, Jecel Assumpcao Jr. <[email protected]>wrote: > John Zabroski wrote: > > > From OO to FPGA: Fitting Round Objects into Square Hardware? [1] > > was one of the interesting talks I sat in on when I attended SPLASH. > > Thanks for the link! > > > I was primarily interested in attending because of VPRI's long-range > > mission and the speculation that FPGA hardware will be fundamental > > to its top-to-bottom, side-to-side late-bound approach. Ian was asked > > about compiling FONC stuff to FPGAs late 2009 [2], and he replied by > > saying FONC loves FPGA concepts but has no FPGA experts and so > > has no concrete plans for using FPGA at the moment [3]. > > Chuck Thacker has been doing interesting (but so far conventional) > things with FPGAs and his work is listed as part of the VPRI efforts in > the anual reports. So I would say there will eventually be results. > > The group I am working with, called the "Reconfigurable Computing > Laboratory", is full of FPGA experts and publishes almost exclusively in > FPGA conferences. > > > Jens Palsberg gave the talk. He proclaimed at the end that this will > > be one of the most important open, hard problems for the next 10 > > years. > > In his case, the bulk of the complexity is hidden inside the AutoPilot > tool created by a third party. I was very shocked that it worked so well > for him. Particularly impressive was getting the Richards benchmark to > fit into a reasonably sized FPGA. > > Most of the state of the art in C-to-hardware is very disappointing. My > own proposal is that if the hardware and software versions of objects > can talk to each other, then you could use adaptive compilation to > convert just the tiny part of the application that has the most effect > on the performance (the "hot spot") into hardware and run the bulk of > the code on a processor. > > > He said that there is a lot of redundancy between the front-end and > > back-end tools and we really need to collapse the two intermediate > > representations used into a single form, because too much information > > has to get reconstructed when you use a subset of the C language as > > an IR. > > True, and every tool has a certain view of the hardware which might not > match an OO model that well. If you look at the Bluespec > (http://www.bluespec.com/) hardware description language, for example, > it deals with very different kinds of objects than Verilog (though it > gets compiled into that) or VHDL. > > > Interestingly, Jens alluded during his talk that it took him 3 years to > > get this work published and he had to refine it to satisfy reviewers. > > My own paper on adaptive compilation for FPGAs was rejected, but I have > to agree with the reviewer's complaints. Some here might have seen it > even so due to friends showing it to friends. > > I don't like the premise that FPGAs as they are now are a given and the > software will have to deal with it, however. This related research into > a different architecture is very interesting, for example: > > http://rala.cba.mit.edu/ > > http://fab.cba.mit.edu/classes/MIT/961.09/04.27/RALA/rala.ppt > > -- Jecel > > > _______________________________________________ > fonc mailing list > [email protected] > http://vpri.org/mailman/listinfo/fonc >
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