Here is a generic VHDL file example. If you need true VHDL files to test the
code explorer, mail me at : pflooo[hat]yahoo[dot fr]. Good luck !
-- Complete example of a generic VHDL file
-- libraries used for the file
library mylibrary1;
library mylibrary2;
-- use of some libraries
use myspecificlibrary1.all;
use myspecificlibrary2.all;
use myspecificlibrary3.all;
-- entity declare the squeleton of the module
-- "mymodule" (inputs and outputs)
entity mymodule is
<...>
end entity;
-- architecture named "architecture1" describes
-- what is in the module "mymodule"
-- may have many architecture in a file
architecture architecture1 of mymodule is
<...>
-- a component named "mycomponent1"
-- could have several component in a file
component mycomponent1
<...>
end component;
<...>
begin
<...>
-- an instance named "myinstance1" of the module "mysubmodule1"
-- (declared in an other library "file1")
-- may have many instances in a file
myinstance1 : entity file1.mysubmodule1
<...>
);
<...>
-- a process named "myprocess1"
-- may have many process in a file
myprocess1 : process (<...>) is
<...>
begin
<...>
end process;
<...>
end architecture;
-- in a file we could declare packages too
-- here the package is named "mypackage1"
package mypackage1 is
<...>
end package;
--
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