Hi, SystemVerilog is a "new" Hardware Description Language that includes Verilog and much more features for assertions and testbenches. I wrote "new" because SystemVerilog is a major extension for the standard Verilog.
SystemVerilog has "adopted" several interesting features from well known languages like VHDL, "e" and PSL and it is intended to be a "universal" Hardware Description Language both for design and verification. You can find further information on http://http://www.systemverilog.org. Cheers. -- <http://forum.pspad.com/read.php?2,37296,37303> PSPad freeware editor http://www.pspad.com
