This message is from the T13 list server.
[Voici the last 4KiB of, yes, less than 16KiB.] > At least all devices I know do so keep track > (hosts are more spotty on this), > and so there is not a problem. Eh? UDma is symmetric? If a bad device behaviour is a problem for reads, then the symmetric bad behaviour by the host is necessarily a problem for writes? > For an individual burst this is never an issue. > So what if the burst was a bit longer than desired? Aye, inside of a block, noone cares. At the edges of blocks, people get into trouble. For example, if you have a four block buffer and someone gets the pausing wrong, you can end up with speed-matching between device and host that works no better than a three block buffer. I know of business-to-business transactions in volume that fell thru because of such issues. I know of chips that revved because someone didn't like their handling of random pauses. UDma's inability to pause at byte boundaries (it can only pause at byte pair boundaries) contributed. > All ASIC designers know to allow enough FIFO space > to make sure any overflows like that can still be > received (indeed, in devices at least the FIFIOs > are often very long nowadays for performance > reasons). I join you in your hope - but not in your trust. > ... If I'm not yet clearer than mud, please consider giving me yet another chance. I'd really love to hear I'm all wrong here. I just don't yet see how this could be, this time. I'm guessing we now soon have to rev the UsbMass standard to accomodate the fact that UDma doesn't count bytes well. In practice, rather than breaking the normal case for hosts that shipped on top of Usb1.1 cores and then tried to run blind on top of Usb2 cores, I imagine we'll choose to sacrifice integrity when not counting bytes well matters. Thanks to UDma. Ouch. at LaVarre Subscribe/Unsubscribe instructions can be found at www.t13.org.
