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Hi all, Jeff mentioned recovery procedures (albeit in a different context), which reminded me. I've been having a look through the ATA-5 specification for DMA recovery procedures. Admittedly I haven't gone over the entire thing, but in the details of the DMA protocol, DMA WRITE commands, and the UDMA CRC stuff, the only references to errors I can find are: 1) "For READ DMA, WRITE DMA, READ DMA QUEUED, or WRITE DMA QUEUED commands: When a CRC error is detected, the error shall be reported by setting both ICRC and ABRT (bit 7 and bit 2 in the Error register) to one. ICRC is defined as the "Interface CRC Error" bit. The host shall respond to this error by re-issuing the command." Is this a requirement, that the host shall keep re-issuing this command? If so, how many times must it fail before the host can reasonably be expected to give up? Presumably (following the note given at the end of the CRC section, reproduced below) it should have fallen back to mode 0 before giving up? Any rules of thumb as to what 'excessive' should mean? :-) "NOTE - If excessive CRC errors are encountered while operating in an Ultra mode, the host should select a slower Ultra mode." Also, in the details of the DMA protocol: 3) "Transition HDMA0:HI0: When the BSY is cleared to zero and DRQ is cleared to zero, then the device has completed the command and shall make a transition to the HI0: Host_Idle state (see Figure 19). If an error is reported, the host shall perform appropriate error recovery." No details on "appropriate error recovery" are given, either in the protocol details or in the command details. Is this purely restricted to the UDMA CRC checking at present, or did I miss something? Thanks, -- Paul STMicroelectronics, Tel: (01454) 462454 1000 Aztec West, Almondsbury, Fax: (01454) 617910 Bristol BS32 4SQ Subscribe/Unsubscribe instructions can be found at www.t13.org.
