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Here is a (I hope) simple DMA example. It does not matter if the physical protocol is MW DMA or U-DMA. Lets assume an ATAPI device with a 25 byte data block. The host wants to execute a Write 10 command of 5 data blocks. That would be a total of 125 data bytes. This would require the host to add a pad byte making it 126 bytes. The host (assuming an x86 PCI bus host) builds a PRD list that could be one PRD, two PRDs, 10 PRDs, none of this matters. The host follows the ATA/ATAPI protocols and selects the devices and sends the PACKET command (with DMA enabled for the data transfer). After decoding the command packet (the Write 10 command for 5 blocks) the device, when ready to transfer data, asserts DMARQ. The host DMA engine response with DMACK and the transfer of the first DMA burst starts. The could be the first and only burst or it could be the first burst of many bursts. Some examples: 1) One burst of 126 bytes. 2) A series of bursts: 30 bytes, 50 bytes, 40 bytes, 6 bytes. 3) A series of bursts: 26 bytes, 26 bytes, 26 bytes, 26 bytes, 20 bytes, 2 bytes. The point here is that the DMA bursts have nothing to do with how the PRD list is build (there may be U-DMA pauses when the host DMA engine fetches a new PRD entry). The point here is that the DMA bursts have nothing to do with the media data block size (there may be U-DMA pauses near data blocks boundaries). But as you can see: with 25 byte blocks there is no way for a DMA burst to contain a single data block. *** Hale Landis *** [EMAIL PROTECTED] *** *** Niwot, CO USA *** www.ata-atapi.com *** Subscribe/Unsubscribe instructions can be found at www.t13.org.
