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On Mon, 17 Dec 2001 13:00:55 -0700, Pat LaVarre wrote: >Yes the text says to read the x1F5:1F4 AtaCylinder (aka >AtapiByteCount) registers ... ... but the diagram per se does >not make the need for this step clear? The "state digrams" are comprised of both the pictures and the words. The pictures and words are one. But I would have no objection to making host reading of the Byte Count more clear in the picture. >Curiously, at first glance, I fail to find a mention of reading >the x1F1 Error register in response to an ERR. Maybe I can hope >more hosts will now learn to tolerate ((x1F1 & xF0) >> 4) != SK >of the following op x03 RequestSense? Good question... But my response is this: A SCSI devcie is allowed to have multiple errors queue up internally. Lets say it has SK=2, a SK=5 and a SK-6 errors all queue up as a result of the command that just ended. Which SK does it put into bits 7-4 of the error register? Does it matter? I can't imagine a host that would act only on the SK in the Error register. I would expect a host to issue Request Sense commands and perform the appropriate SCSI error recovery for each non-zero SK it receives.. *** Hale Landis *** [EMAIL PROTECTED] *** *** Niwot, CO USA *** www.ata-atapi.com *** Subscribe/Unsubscribe instructions can be found at www.t13.org.
