I'm trying to figure out what I need to do with the ERROR register in the event of an Ultra DMA data
transfer CRC error being detected by an ATAPI (Packet) device.
In ATA-ATAPI 6 rev 3a section 9.15 Ultra DMA CRC rules I see two cases that apply to my situation,
but where I don't fully understand what I need to do:
Request Sense Packet Command, and non Request Sense Packet command.
First case:
For the Request Sense Packet Command, I see that if a CRC error is detected by the device
during the transmission of sense data that it should complete the command with the check
condition (STATUS register bit 0 = '1'). The device shall report a sense key of 0xB {Command
Aborted} (presumably in the ERROR register bits 7 down to 4).
Should the device also set the abort bit (ERROR register bit 2) = '1'?
Second case:
For the non Request Sense Packet Commands, I see that if a CRC error is detected by the device
during the transmission of data that it should complete the command with the check condition
(STATUS register bit 0 = '1'). The device shall report a sense key of 0x4 {Hardware Error}
(presumably in the ERROR register bits 7 down to 4).
Should the device also set the abort bit (ERROR register bit 2) = '1'?
If I understand things correctly the ICRC bit (ERROR register bit 7) should not be set by an ATAPI (Packet)
device, is this assumption correct.
Many thanks in advance
John
