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On Thu, 03 Jan 2002 16:07:31 -0700, Pat LaVarre wrote: >> > One byte count that matters >> > is the count of bytes written or read that the OS reports to the app. And I hope the device drivers in your favorite OS report the correct value. This has nothing to do with the ATA/ATAPI physical interface (or the SCSI or OHCI/1394 physical interface). >> > Another byte count that matters >> > is the count of bytes actually written or read. And this number is the number of bytes the device wants/needs to transfer given the contents and/or parameters of the current command. For ATA/ATAPI there is a general requirement that the ATA/ATAPI host also expects to transfer the same number of bytes (plus a pad byte in some cases). I think part of the confusion here is that in some cases (like that of x86 DMA) there is yet another byte count: the byte count programmed into the DMA engine (for PCI that would be via the PRD list). Pat: I think you have been confusing the last two. And perhaps you have been saying that some OS drivers do not program the DMA engine with the correct byte count. And I think you may have confused "data in" commands with "data out" commands in some emails. > iocb x 12 0 0 0 FF 0 /i x1000 > Now suppose the device under test > makes x91 bytes of Inquiry data available. > With an AtapiPio device we see the host copies in x91 bytes. First let me say this is a "data in" example and I don't think it will show the problem you are trying to explain? I will assume you mean that the total DRQ data block BC values is either 91H and that the host does the appropriate number of reads of the ATA/ATAPI Data register. So when the host performs the actual I/O reads of the ATA/ATAPI Data register 92H bytes are transferred. What happens to the pad byte at the end is completely and totally up to the OS drivers and the application receiving the data. > With an AtapiDma device we see the host copies in x92 bytes. For Multiword DMA: a) If the x86 host DMA engine is programmed to transfer 92H bytes (that is because the old MW DMA engines used only "word counts" not "byte counts"). The last byte is a pad byte. Again what happens to that pad byte is up to the OS drivers or the application. b) If the x86 host DMA engine is programmed to transfer less than 92H bytes there is a hung device condition probably leading to a timeout error. c) If the x86 host DMA engine is programmed to transfer more than 92H bytes then the command will end when the device stops transferring data at the end of the command (the device deasserts DMARQ and has BSY=0 DRQ=0 status and maybe asserts INTRQ). In this case the host DMA engine will have read 92H bytes from the device. Again the last byte is a pad byte and what happens to it is up to the OS drivers or application. For Ultra DMA: Just reproduce everything said for MW DMA above... There is NO difference. (OK, there is a difference... With the old x86 DMA engine the OS driver could determine how many bytes (words)that were transferred... It is not possible to do this with today's stupid PCI bus ATA host adapters!) >If we can't agree something as plainly broken as this is a problem ... There is nothing broken here... In fact in this example there is NO difference between PIO, MW DMA and Ultra DMA. All are the same (assuming a correctly implemented host). There is a pad byte at the end of the data PIO data transfer, there is a pad byte at the end of the MW DMA transfer, there is a pad byte at the end of the Ultra DMA transfer. >Does everyone out there really think we don't care >precisely how many bytes the host copies per command? >Really??? The number of bytes transferred is precise in all cases above. The example command transferred 91H bytes in all cases and in all cases there is a pad byte to make it 92H bytes. > Basically, can you provide data that shows an actual problem here? Whatever that data is or whatever that example is, it is NOT the example you provided in this email. Again have you confused "data in" commands with "data out" commands? But let me ask this question: Are you concerned about the fact that in this example in PIO mode the device told the host it had 91H bytes of data (but transferred 92H bytes) while in DMA mode it did not say how many bytes it had but it transferred 92H bytes? Are you concerned that the host (OS drivers) might not realize that in DMA the last byte is a pad byte? If the host did not realize that the last byte is a pad byte then that would be broken host (in my opinion). *** Hale Landis *** [EMAIL PROTECTED] *** *** Niwot, CO USA *** www.ata-atapi.com *** Subscribe/Unsubscribe instructions can be found at www.t13.org.
