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Pat, I don't know what to do... It sure looks like you have made incorrect assumptions about what the ATA/ATAPI-x documents say and how ATA/ATAPI PIO and DMA are implemented. And I think you are trying to say that T13 has a problem because you see hosts and devices doing things that are different than the way you interpret the T13 documents. Please let me know what part(s) of this email troubles you. Thanks! You keep talking about a SCSI Inquiry command issued to an ATAPI device in PIO or DMA mode. The CDB asks the target device to transfer the first 5 bytes of the Inquiry data. Lets get some things out of the way so we can discover what it is you are really talking about: a) The ATA interface data transfers are done 16-bits (2 bytes) at a time in PIO and DMA. b) A command that requests an odd number of bytes will result in one more byte being transferred in eitehr PIO or DMA. For you example, in PIO or DMA, the device has no choice but to transfer 6 bytes of data. That last byte is a pad byte. On the x86 host side for PIO the software has no choice but to use the REP INSW or REP INSD instructions. The host side using PIO has no way to suppress the transfer of the pad byte. If the PIO host used REP INSD it would get 3 pad bytes and two of those bytes would be pad bytes from inside the host controller hardware! On the x86 host side for DMA the host side DMA engines we use today can only be programmed to transfer an even number of bytes. Does this matter? No, because the SCSI CDB tells us only 5 bytes are valid data. c) Yes, in PIO the device provides a Byte Count for each DRQ data block. And SFF-8020 and ATA/ATAPI encourage devices to indicate a odd sized data transfer by having an odd Byte Count for the last DRQ data block. But is that required? Maybe, maybe not. Because the host and device knows it is not possible to transfer an odd number of bytes, the host and device know that it must add one to any odd Byte Count. At the lowest level of the ATA/ATAPI protocol and at the x86 PIO and DMA data transfer hardware level all transfers are an even number of bytes. Yes, I do expect ATAPI device to have a total PIO byte count of 5 for you example. But if the byte count from the device is 6, what is the problem? Well... There is no problem because the SCSI CDB tells both host and device that only the first 5 bytes are used and that the last byte is a pad byte. And now let me repeat what I said in my previous email(s). The total data transfer for an ATA or ATAPI command is viewed as a single stream of data. Where the media data blocks are within that data stream is not important. Only in ATA PIO does the DRQ data block boundaries seem to correspond to the media data block boundaries. In ATAPI PIO the DRQ data blocks are not required, and usually do not, have any relationship to the size of device media data blocks. In ATAPI DMA the DMA data bursts are not required, and usually do not have, any relationship to the size of device media data blocks. In both PIO and DMA the last word (byte) of a DRQ data block or DMA data burst are followed by the first word (bytes) of the next DRQ data block or DMA data burst. There are no extra bytes or bytes that can be ignored at the boundary between DRQ data blocks or DMA data burst. While I'm writing this your most recent message arrived. In it you say: >I can try to echo what I hear you saying - but your examples >here now leave me without line-by-line commentary to offer >because they seem to me to be artificially constructed >to duck the real issue. Yes, you may not find a real world host and device that do exactly what my example shows but there should be nothing invalid about my example. I wish you would look at it and comment... Do you think it show a valid Ultra DMA transfer? And what real issue does it fail to show? Please tell us! I know that if my example is invalid then Jim or Michael or someone will tell us. Summary: For data transfers that are odd length I think you are trying to say that host software and hardware design restrictions are a T13 problem. Sorry, but the fact that a x86 PIO and DMA host side is unable to transfer anything but even length blocks or bursts of data is not a T13 ATA/ATAPI problem, maybe it is a T13 "host adapter standard" problem? For data transfers of "block data" I think you want DRQ data blocks and DMA data burst to exactly conrrespond to the size of device media data blocks. But it doesn't work that way. There are no extra bytes or bytes that can be ignored at the boundary between DRQ data blocks or DMA data burst. *** Hale Landis *** www.ata-atapi.com ***
