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> Re: [t13] on residue - short, concrete, reproducible? > From: Hale Landis > Date: Saturday - April 13, 2002 11:10 AM ... > You keep talking about a SCSI ... > command issued to an ATAPI device > in PIO or DMA mode. Yes. I'm claiming the Pio/Dma design choice has significant actual consequences beyond those that arise from raising the burst data transfer rate. > Lets get some things out of the way Let's! Curiously, I find here I say yes, yes, yes, ... but then I say No. Maybe that No is my key mis/understanding. > a) The ATA interface data transfers > are done 16-bits (2 bytes) at a time in PIO and DMA. Yes Pio and Dma clock N * 2 bytes across the bus. > b) A command that requests an odd number > of bytes will result in one more byte > being transferred in eitehr PIO or DMA. Yes to copy N * 2 - 1 bytes across a 2 byte wide bus the host & device have to clock N * 2 bytes across the bus. > If the PIO host used REP INSD > it would get 3 pad bytes Yes, to copy N * 4 - 3 bytes, the host & the device have to add 3 pad bytes when either rudely insists on involving a bus engine that can only copy N * 4 bytes. > On the x86 host side for DMA > the host side DMA engines > we use today can only be programmed > to transfer an even number of bytes. Yes some x86 Atapi Dma engines can copy only N * 2 bytes. I have been told others can copy only N * 4 bytes. I imagine soon we will hear of hosts that can copy only N * 8 bytes. > The host side using PIO > has no way to suppress the > transfer of the pad byte. No. Hosts vary in quality of implementation. > On the x86 host side for PIO > the software has no choice > but to use the REP INSW > or REP INSD instructions. No. Indeed yes REP INSW and REP OUTSW copy only "word"s of data between i/o and memory pace. But x86 also offers a simpler, slower, form of byte and word i/o double-buffered thru the cpu registers. I think I remember the ASM syntax is IN AL,DX for byte-wide access and IN AX,DX for word-wide access. Here the copy to/from i/o space is from/to cpu registers rather than from/to memory. In practice, I see Microsoft Win98 & WinMe copy just N * 2 - 1 bytes between i/o and memory any time an AtapiPio device asks to copy D = N * 2 - 1 <= H bytes, where H is the count of data buffer bytes allocated. I've heard the Microsoft implementation for copying N * 2 - 1 bytes In double-buffers via REP INSW of N * 2 - 2 bytes followed by an IN AX of a two byte "word" followed by a MOV of just one of those bytes. AL I think, but maybe it was AH. I find (REP INSW, delay, IN) a little bit rude. I'd rather see a host smoothly and evenly REP INSW N * 2 bytes into an secondary buffer, and then copy N * 2 - 1 bytes from memory to memory. However it's done, the end result with Microsoft clearly is that only N * 2 - 1 bytes are smashed by a copy In. I hope, symmetrically, only N * 2 - 1 bytes are accessed by a copy Out, else maybe we've got page faults lurking out there. > or REP INSD instructions. I hear that x86 REP INSD of Ata/pi data commonly doesn't work: the bus trace the device sees doesn't match what appears in memory. I've seen utilities with REP INSD options. I hear REP INSD bursts data more quickly than REP INSW some of the time when REP INSD isn't corrupting the data it copies. > You keep talking about a SCSI ... > command issued to an ATAPI device in PIO or DMA mode. Back in the real world, Pio works where Dma doesn't. Why not, how often not, who can fix it, who if anyone should fix it ... those are our questions. Pat LaVarre
