This message is from the T13 list server.
I thought PAUSE and TERMINATE (for UDMA) can only happen at WORD
boundaries. The UDMA hardware is not confused by odd byte counts....
They don't exist.
The UltraDMA hardware already seems to know how to pause and resume
properly. That stuff is transparent to the host. It seems to me that a
"bridge" device also needs to handle this stuff transparently without
requiring ANY change to the host or to the device.
...Harlan
On 4/15/02, Hale wrote:
>This message is from the T13 list server.
>
>
>Something more to think about when attempting to transfer a BC value
>from the device to the host within each DMA data burst...
>
>The BC values needs to be transmitted at the end of the DMA burst
>around the same time the CRC is transmitted. This is because the BC
>for the current DMA burst is not known until the end of the DMA
>burst. This is because the host or device are able to terminate DMA
>bursts at any time (for any reason). For example, the device might
>want to transfer a 1000 bytes, the host might stop the transfer after
>only 50 bytes. {This is much different that PIO bursts. In PIO the BC
>value is the number of bytes the host SHALL transfer for the current
>DRQ data block.} For this new DMA BC to be valid the device can not
>send it to the host until the end of the DMA burst. And to have the
>same effect as the PIO BC this new DMA BC must be sent from the
>device to the host for both read and write DMA transfers.
>
>Comments?
>
>
>
>*** Hale Landis *** www.ata-atapi.com ***
>
>
>
