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Larry; If I look at the ATA Spec "SRISE" in the table of AC characteristics is 1.25V/ns for the rise time for less than UDMA Mode 4. It also states that its for "any signal". I deem this to include RESET. Fall Time is not mentioned, but is it really needed. Also the RESET is defined as a Totem Pole attached signal. I also now the the RESET is not a edge level triggered signal. When we increase the UDMA mode above 4 the Rise Time changes and the Fall Time is now included, but this is for only for DD(0-15) and STROBE. Note 1 is mentioned in each case. I leave that to the reader. I conclude that the ATA specification, could be clearer and specific is all applicable data transfer modes for all signals. Thanks Tom Colligan > From: Larry Barras <[EMAIL PROTECTED]> > Date: Thu, 12 Dec 2002 14:12:44 -0800 > To: [EMAIL PROTECTED] > Subject: [t13] Rise time of HRESET de-assert? > > This message is from the T13 list server. > > > In reading the spec, I have a question regarding the rise time of the > ATA Hard Reset line. What is it? There's a specified minimum hold > time of 25 �s, but nothing regarding the rise and fall times of the > signal. > -- > > --------------------- > I make stuff go. > --------------------- > > Larry Barras > Apple Computer Inc. > 1 Infinite Loop > MS: 306-2TC > Cupertino, CA 95014 > (408) 974-3220
