Constantine Sapuntzakis raised this issue a couple of months ago and yesterday at the T13 meeting we came up with a correction to the Host Side Packet DMA state diagrams that appear in ATA/ATAPI-5, 6 and the current draft of 7.
The correction has two parts:
1. Add a further condition to HPD2:HPD4 that "nIEN=1".
2. Add a transition HPD3:HPD4 with condition, "DMARQ asserted".
The diagram will be published in its corrected form in ATA-7. The committee is considering an errata for ATA-5 and ATA-6.
At 11:06 AM -0800 4/5/03, Constantine Sapuntzakis wrote:
This message is from the T13 list server.
Figure 33 on page 350:
The HPD1:HPD3 transition is not in SFF 8020i r2.6 and seems inconsistent with the device diagram in Figure 34.
The transition seems to imply that the host should wait for an interrupt before starting a DMA transfer. But in the device diagram (Figure 34), no such interrupt is generated prior to a DMA transfer.
Also, SFF 8020i r2.6 does not require device to assert an interrupt before starting a packet DMA (according to page 35)
-Costa
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