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Hi,

I'm looking at the "Host PACKET non-data and PIO data command state diagram"
(figure 53 in d1532v2r4.pdf). I'm ignoring the overlapped modes, and I'm
assuming nIEN=0.

In this case, if i follow the diagram and the text, after transfering a data
block in HP4 I have to go back to HP2, and from HP2 i'm confused as to in
which case i should do the HP2:HP3 transition. All the transitions from HP2
doesnt seem excluding one another. 
In particular, if I look at the condition on BSY ans DRQ we have:
BSY=0; DRQ=0 : HP2:HI0
BSY=0; DRQ=1 : HP2:HP4
BSY=1; DRQ=0 : HP2:HP2 
BSY=1; DRQ=1 : ???

If I compare to the PIO protocols, we always go back to the INTRQ_Wait state
directly after the Transfer_Data state (in the case nIEN=0) but this one
always go back to the Check_Status.

Is there a rationale for that?

Thanks

-- Fabrice

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