This message is from the T13 list server.
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when Time-Limited Commands was removed from ATA/ATAPI-7.
Re; the ERROR register
Before TLC was included (d1532v2r0c.pdf, section 9.9.3)
The contents of this register shall be valid when BSY and DRQ are
cleared to zero and ERR is set to one.
After TLC was removed (d1532v1r4.pdf, section 5.7.2)
The contents of this register shall be valid when BSY and DRQ are
cleared to zero and either ERR or SE isset to one.
Please note:
* 'isset'
* 'either ERR or SE'
Thank You !!!
-----------------------------------------------------------------
Jim Hatfield
ATA Interface Firmware & T13 (ATA/ATAPI) Standards Representative
Seagate Technology - PSG
e-mail: [EMAIL PROTECTED]
s-mail: 389 Disc Drive; Longmont, CO 80503 USA
voice: 720-684-2120
fax : 720-684-2711
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| | "John Masiewicz" |
| | <[EMAIL PROTECTED]|
| | dc.com> |
| | Sent by: |
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| | rg |
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| | 04/14/2004 10:16 |
| | AM |
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| To: "Eschmann, Michael K" <[EMAIL PROTECTED]>, <[EMAIL PROTECTED]>
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| cc:
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| Subject: RE: [t13] ABRT bit usage in SATA
|
>--------------------------------------------------------------------------------------------------------------|
T13,
I have also been looking into the definition of ABRT, since there was some
confusion over the difference of the various uses of terms Abort or Command
Abort, and similar undefined terms. The Error Register states the
definition for ABRT is:
Bit 2 - ABRT (command aborted) is set to one to indicate the requested
command has been command aborted because the command code or a command
parameter is invalid, the command is not supported, a prerequisite for the
command has not been met, or some other error has occurred.
Note that ABRT is the ONLY bit in the Error register that is NOT command
dependent.
I was wrong in my original thinking that ABRT did not necessarily mean
Command Aborted (discussed in SATA topic). In fact, the term Command
Aborted is a defined term, and it states:
command aborted: Command completion with ABRT set to one in the Error
register and ERR set to one in the Status register.
But remember the old rule:
The contents of this register shall be valid when BSY and DRQ are cleared
to zero and either ERR or SE is set to one.
I think the definition, validity rules, and use of the bit ABRT and the
term "command aborted" are fairly clear, and should not cause reason for
confusion in SATA. It is true as you state, and as stated in the SATA
topic, that the careless use of the term Aborted is a problem that needs to
be cleaned up. In the specific command descriptions you indicated, the
added condition for ICRC error seems to be to ensure that setting ICRC does
not eliminate the need to set ABRT.
Furthermore, We were aware of some inconsistencies between pATA and SATA
definitions, including signal usages versus FIS's, and bit definitions. It
was deemed an enormous task to try to correct it all in one big project.
Much of this work is outlined in the ATA-8 project, and that's where I
think it will have to be done. In order to acknowledge this reality, we
added the statement in ATA-7 (vol 1, clause 5.1):
References to parallel implementation bus signals (e.g. DMACK, DMARQ, etc)
apply only to parallel implementations. See Volume 3 for additional
information on serial protocol. Some register bits (e.g. nIEN, SRST, etc.)
have different requirements in the serial implementation (See Volume 3).
I do not think that there is sufficient difference (if any) between SATA
usage and pATA to warrant much concern.
I will also post this response to the SATA Digital reflector for comments
John Masiewicz
Western Digital
________________________________
From: [EMAIL PROTECTED] [mailto:[EMAIL PROTECTED] On Behalf Of
Eschmann, Michael K
Sent: Tuesday, April 13, 2004 6:38 AM
To: [EMAIL PROTECTED]
Subject: [t13] ABRT bit usage in SATA
Folks,
The ATA7 document describes error responses for all data commands with an
interesting side-effect. In all read or write commands the following abort
definition exists:
ABRT shall be set to one if this command is not supported or if an
error, including an ICRC error, has occurred during an Ultra DMA data
transfer.
With the inclusion of SATA does the "Ultra DMA" text get expanded to
include SATA? If not, then why not?
Thanks,
Michael K. Eschmann
Intel Americas, Inc.
TMG, I/O Architecture Lab
816-524-7418 (alt -7215)
