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Question about using the DEV bit in the Device register. The spec says device register indeterminant if written to when DRQ or BSY bit is 1.
Good to hear.
I like to see ATAPI and ATA devices left free to work to keep the three DEV caches in sync.
You know the three caches I mean? The host and device 0 and device 1 each maintain an independent idea of what the DEV bit should be - that's three caches, which is more than one, which implies cache incoherence on occasion in practice.
Some kinds of reset by definition synchronise those three cache to agree DEV is zero within a bounded delay.
Writes with DRQ and BSY both clear keep those cache in agreement.
Other kinds of writes of DEV have less determinate effects. I remember arguing that letting the write take effect in practice keeps the host and that device in sync, which is goodness, because then all cache are in sync if the other device is absent, without having harmed the situation when the other is present. I often see people check BSY but not DRQ.
What about for overlap commands
I have no clue sorry.
when the DEV bit in the Device register needed to be changed while DRQ or BSY can be asserted?
Pat LaVarre
