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Yes. You are right, this is poorly worded and an error. Bits 3-0 must be read only in order to guarantee at least 16 bytes of I/O space. There is also potential application interaction problems (certain OS's will not allow you to have > 16 bytes here) if this register is any larger than that. (Which should probably be noted). At the meeting last week I agreed to bring a proposal to write up HBA-2 (to include parallel emulation on SATA (to standardize behavior and correct some problems that are in ATA-7). I will also write up an errata proposal for this for the original HBA proposal. Thanks for catching this! -----Original Message----- From: [EMAIL PROTECTED] [mailto:[EMAIL PROTECTED] On Behalf Of Tom Sylla Sent: Tuesday, March 01, 2005 1:51 PM To: [email protected] Subject: [t13] Host Adapter Spec This message is from the T13 list server. I see this in Rev 1.0 (Jan 17, 2003) of 1510D (Host Adapter Spec) ---------------- 6.6.2.5 PCI Base Address Register (BAR) 4 Base address of the ATA Bus Master I/O registers. Address Offset 20h Default Value 00000001h Attribute Bits 31-16 may be Read Only, Bits 15-3 Read/Write, Bits 2-0 Read Only. Size 32 bits ---------------- and then this just below that: ---------------- The bus master -ATA function uses 16 bytes of I/O space. All bus master -ATA I/O space registers can be accessed as byte, word, or Dword quantities. The base address for these registers is PCI BAR 4. The description of the 16 bytes of I/O registers follows: ---------------- If bits 15-3 are Read/Write, and Bits 2-0 are read only as 001, then how is one supposed to access all 16 bytes of I/O space? Shouldn't bits 3-0 be read-only, and 15-4 be R/W? If I size a PCI IDE Bus Master BAR 4 on any platform I can find, I get FFFFFFF1 instead of FFFFFFF9. If this is an error, is it wrong in the "official" 1510D? Thanks, Tom Sylla
