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Dear all, All commands which use Data register for data transfer use only DD[7:0] in 8-bit PIO transfer mode. DMA commands use the 16-bit Data port to transfer data. for devices not implemented with PACKET feature set. I want to make sure that whether DMA commands should be accepted or aborted in CFA devices with 8-bit PIO data transfer mode enabled. According to section 6.2.1.15 on page 130 of "CF+ and CompactFlash Specification Revision 3.0", it mentinos that "When a Read DMA command is received by the Card and 8 bit transfer mode has been enabled by the Set Features command, the Card shall return the Aborted error". I think the PIO Word Data Register and DMA Word Data Register described on page 99 of CFA3.0 spe. correspond to Data Port and Data register described on page 65 of ATA/ATAPI-6, respectively. The architecture between CFA and ATA devices are pretty similar. The purpose of 8-bit data transfer mode is for the compatibility of old host controllers which have only 8-bit data bus width to access devices. To prevent system hang, the device which has 8-bit mode enabled aborts DMA commands, which requier 16-bit for data transfer. ATA/ATAPI-6 specficiation does not have the specific descriptions for the handling of DMA commands in 8-bit mode for devices supporting the CFA feature set, but CFA 3.0 specification does abort DMA commands in 8-bit mode. Is DMA READ command aborted or DD[15:0] bus used for data transfer when the ATA device receives the DMA READ command with CFA 8-bit transfer mode enabled? Best regards, Kepler
